Circuit level interconnect reliability study using 3D circuit model

Modeling the effect of barrier thickness and low-k dielectric on circuit reliability using 3D model

“…3. The detailed steps for the 3D model construction from the 2D layout and the setup for the transient thermal-electric and structural-thermal simulation can be found in our recent work [15,16].…”

“…The impact of various driving forces on electromigration in a 3D circuit model under typical operating condition using both Cadence (a circuit simulator) and ANSYS (a finite element software) was analyzed in our earlier work [15,16]. The maximum atomic flux divergence (AFD), which determines the void formation location and the EM lifetime of inter-connections in a circuit [17,18] are derived based on the thermal-electric and structural-thermal simulation result.…”

Effect of IC layout on the reliability of CMOS amplifiers

“…Due to the scale of the 3D model, we are only looking at the void initiation location, and hence microstructure and stress relaxation effect can be ignored. The detailed steps for constructing the 3D model from the 2D layout, the material properties, the setup for the electric-thermal-structural simulation, and the equations and the procedures for the calculation of the atomic flux and atomic flux divergence (AFD) can be found in our recent works [16,17].…”

“…6. Under normal circuit operation condition, the total AFD depends on the AFD due to thermo-mechanical stress gradient migration (AFD_SM), which in turn depends on the product of the thermo-mechanical stress gradient and the temperature gradient [17,18]. The uniform pattern of the contacts of Layout 2a, and the large difference between the operating temperature and the stress free temperature of the interconnects causes similar values of the thermo-mechanical stress gradient for the models with different number of contacts.…”

“…[16][17][18], we expand our work with more significant layout modifications, such as the change in the finger number and the placement of the transistors. The layout that can most effectively enhance the circuit reliability is studied.…”