Circuit-Level Layout-Aware Modeling of Single-Event Effects in 65-nm CMOS ICs

Balbekov, Anton O.; Gorbunov, Maxim S.; Зебрев, Г. И.

doi:10.1109/tns.2018.2802205

Cited by 12 publications

(3 citation statements)

References 26 publications

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“…It is likely to cause voltage transients at the nodes [8,9,10,11,12,13]. If the voltage transients occur at the storage nodes of latches, the data stored might be flipped [7,14,15,16,17,18].…”

Section: Introductionmentioning

confidence: 99%

A single event upset tolerant latch with parallel nodes

Liu

Lin

et al. 2019

IEICE Electron. Express

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A single event upset (SEU) tolerant latch has been put forward in the current paper. By means of the parallel nodes structure design together with the layout-level optimization design, the proposed design is capable of substantially improving the immunity to SEU. In comparison with the conventional latch, the stacked latch with isolation and the dualmodular-redundancy (DMR) latch with C-element, the simulation results based on the 65 nm CMOS process demonstrate that the proposed latch performs much better in SEU mitigation. For P-hit simulation, the proposed latch can achieve a correct output in the end, no matter the struck PMOS is at OFF state or ON state. For N-hit simulation, the proposed latch is also capable of mitigating the voltage transient and recovering to original state eventually.

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Section: Introductionmentioning

confidence: 99%

A single event upset tolerant latch with parallel nodes

Liu

Lin

et al. 2019

IEICE Electron. Express

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show abstract

“…Applying dual modular redundancy or dual-interlocked storage cell (DICE) [6], HiPeR (High Performance Robust) latch presented in [7], and HLR-CG1 (High performance, Low cost and Robust Clock Gating) latch proposed in [8] can tolerate the disturbance of SEU. However, for advanced CMOS technologies, the proximity of devices by scaling can result in charge collection and sharing at multiple nodes from a single high-energy particle strike [9]. These existing schemes proposed for tolerating SEU or single upset (SU) can no longer be robust in face of double upsets (DUs).…”

Section: Introductionmentioning

confidence: 99%

“…These existing schemes proposed for tolerating SEU or single upset (SU) can no longer be robust in face of double upsets (DUs). Well isolation, guard rings and layout techniques were utilized to solve the multiple upsets caused by charge sharing, but benefits of these techniques are quite limited [9,10]. In order to solve this severe problem, researchers have proposed plenty of latches which can effectively tolerate the DUs [11][12][13][14][15][16][17].…”

Section: Introductionmentioning

confidence: 99%

A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

et al. 2018

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Single event double upsets (SEDUs) caused by charge sharing have been an important contributor to the soft error in integrated circuits. Most of the up-to-date double-upset (DU) tolerant latches suffer from high costs in terms of delay, power and area. In this paper, we propose a novel high-performance low-cost double-upset tolerant (HLDUT) latch. Simulation waveforms have validated the double-upset tolerance of the proposed latch. Besides, detailed comparisons demonstrate that our design saves 805.24% delay-power-area product (DPAP) on average compared with other considered up-to-date double-upset tolerant latches, which means the proposed latch is a promising candidate for future highly reliable low-cost applications.

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Deep insight on efficiency of deposited energy within sensitive volumes for characterizing basic mechanism of single event upset saturated cross-section regarding implicit inaccuracy

Geng,

Tong

2023

Radiation Effects and Defects in Solids

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Circuit-Level Layout-Aware Modeling of Single-Event Effects in 65-nm CMOS ICs

Cited by 12 publications

References 26 publications

A single event upset tolerant latch with parallel nodes

A single event upset tolerant latch with parallel nodes

A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

Deep insight on efficiency of deposited energy within sensitive volumes for characterizing basic mechanism of single event upset saturated cross-section regarding implicit inaccuracy

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