Circuit optimization for minimisation of power consumption under delay constraint

Abstract

We address the problem of optimization of VLSI circuits to minimize power consumption while meeting performance goals. We present a method of estimating power consumption of a basic or complex CMOS gate which takes the internal capacitances of the gate into account. This method is used to select an ordering of series-connected transistors found in CMOS gates to achieve lower power consumption. We describe a multipass algorithm which makes use of transistor reordering to optimize performance and power consumption of circuits and which has a linear time complexity per pass. The algorithm has been benchmarked on several large examples and the results are presented.

Optimization of Power Consumption in VLSI Circuit

“…Ordering of gate inputs affect both power and delay. Prasad [1] has described methods to optimize the power and/or delay of logic gates based on transistor reordering. So, considerable improvements in power and delay can be obtained by proper ordering of transistors.…”

Power minimization in IC design

“…The rationale is that this transistor will switch off more frequently, thus blocking the internal nodes from non-productive charging and discharging. Another rule is presented in [114] where the input that has the highest switching activity when all other inputs are set to their non-controlling values (one for NMOS and zero for PMOS in series-connected transistors) is directed to the input closest to the output terminal. The rationale is that assigning such a signal closest to the V dd and ground terminals would lead to large power dissipation.…”

A power modeling and characterization method for the CMOS standard cell library

“…Given the input signal probabilities and transition densities of the original complex gate, the equivalent input signal probabilities and transition densities of the simplified circuit can be calculated according to [4]. After obtaining the simplified circuit, we build the corresponding STGPE.…”