Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

Asthana, Vivek; Kar, Malathi; Jiménez, José Luis Ubera; Noël, Jean-Philippe; Haendler, S.; Galy, Philippe

doi:10.1109/esscirc.2013.6649161

Cited by 11 publications

(5 citation statements)

References 17 publications

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“…11, which shows the bitcell integrity during a retention phase for a temperature range between −10°C and 125°C and for supply voltages of 0.8 and 1 V. The fail percentage versus the V T gap between the pMOS and nMOS are shown. Note that we have a robust retention with a 180-mV gap for V DD = 0.8 V and 210 mV for V DD = 1 V. These V T gaps are obtained thanks to knobs (process and design) offered by the FD-SOI technology: the gate type combined with the backplane type [20] and backbiasing (BB) technique [21].…”

Section: In-house Testbench and Simulation Resultsmentioning

confidence: 82%

High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

Boumchedda

Noël

Giraud

et al. 2017

IEEE Trans. VLSI Syst.

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In this paper, we present a high-density fourtransistor (4T) static random access memory (SRAM) bitcell design for 3-D CoolCube technology platform based on 14-nm fully depleted -silicon on insulator MOS transistors to show the compatibility between the 4T SRAM and the 3-D design and the considerable density gain that they can achieve when combined. The 4T SRAM bitcell has been characterized to investigate the critical operations in terms of stability (retention and read) taking into account the postlayout parasitic elements. Thus, failure mechanisms are exposed and explained. Based on this paper, a data-dependent dynamic back-biasing scheme improving the bitcell stability is developed. A specific read-assist circuit is also proposed in order to enable a large number of bitcells per column in a memory array. Finally, the designed bitcell offers up to 30% area gain compared to a planar six-transistor SRAM bitcell in the same technology node.

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Section: In-house Testbench and Simulation Resultsmentioning

confidence: 82%

High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

Boumchedda

Noël

Giraud

et al. 2017

IEEE Trans. VLSI Syst.

Self Cite

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“…The time in between refreshes is defined as retention time. ST [3] IBM [4] Reneseas/Ko [9] EPFL [10] UM/LDPC [11] Hitachi [12] STARC [13] Intel/Memory [14] UM/Biomedical [15] EPFL/Biomedical [16] Samsung/Camera [17] Industrial Products…”

Section: B Retention Time (Rt)mentioning

confidence: 99%

Modem Gain-Cell Memories in Advanced Technologies

Amat

Canal

Rubio

2018

2018 IEEE 24th International Symposium on on-Line Testing and Robust System Design (IOLTS)

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With the advent of the slowdown in DRAM capacitor scaling [1] and the increased reliability problems of traditional 6T SRAM memories [2], industry and academia have looked for alternative memory cells. Among those, gaincells have attracted significant attention due to their smaller size (compared to SRAM) and non-destructive read operation (compared to DRAM) as well as considerable low power and reasonable robustness. This paper first summarizes the available evidences of SRAM and eDRAM in commercial and test chips. Then, it analyzes the performance, reliability and scaling of eDRAM gain-cells in 10 and 7 nm FinFET technology; as well as above and below VT (i.e. sub-threshold).

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“…An example is given by the feasibility of a 4T bitcell studied in [6]. A 4T bitcell consists of a pull-down nMOS driver and a pMOS access transistor, where the leakage of the access transistor holds the "1".…”

Section: Memoriesmentioning

confidence: 99%

FD-SOI Technology Development and Key Devices Characteristics for Fast, Power Efficient, Low Voltage SoCs

Hartmann

2014

2014 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)

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Electronics is more and more pervasive in everyday life: smartphones, connected cars, Internet of Things… All this is not only about mobile energy efficient technologies: it is wireless and wireline connectivity, sensors. UTBB FD-SOI (Ultra Thin Body and Buried-oxide Fully Depleted Silicon On Insulator) is a planar semiconductor technology that introduced the advantages of fully depleted transistors from the 28nm technology node, which is cost optimal, allowing joining the advantages of a general purpose high speed technology with the ones of a low power one. The paper describes the development of the FD-SOI technology, the choice of devices centering, and their main characteristics, especially suited for high speed energy efficient operation, even in low voltage conditions, thanks to the their intrinsic characteristics offered by being fully depleted. Those, are not limited to digital logic devices, but extend to memory bit-cells (fast, low leakage, and operating at low voltage) and the exceptional analog characteristics of devices.Index Terms -UTBB FD-SOI, ARM Cortex A9, forward body-bias

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Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

Cited by 11 publications

References 17 publications

High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

High-Density 4T SRAM Bitcell in 14-nm 3-D CoolCube Technology Exploiting Assist Techniques

Modem Gain-Cell Memories in Advanced Technologies

FD-SOI Technology Development and Key Devices Characteristics for Fast, Power Efficient, Low Voltage SoCs

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