Circulating current reduction of a grid-connected parallel interleaved converter using energy shaping control

Abbès, Mohamed Slim; Mehouachi, Ines; Chebbi, Souad

doi:10.1016/j.epsr.2019.01.020

Cited by 4 publications

(9 citation statements)

References 18 publications

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“…The DPC based conventional SVPWM of PWM Rectifier (DPC-CSVPWM) technique is based on the direct control of active and reactive powers to generate the reference voltage at the input of the CSVPWM block by using closed -loop power controllers, as shown in Fig. 5 [26]. For unity power factor, the reactive power reference is set to zero and the active power reference represents the injected power on the DC side from the AC side and is determined by the DC-bus voltage regulation.…”

Section: Active and Reactive Power Control Loopsmentioning

confidence: 99%

“…The active power reference * x P can be expressed as [26]: (18) where pdc k and idc k are the proportional and integral parameters of the closed-loop DC-bus voltage PI controller, and are calculated using pole placement method as: The closed-loop DC-bus voltage obtained according to Equation ( 18) is shown in Fig. 6.…”

Section: Pi Control Of the Dc-bus Voltagementioning

confidence: 99%

“…As shown in Fig. 7, each CSVPWM's reference voltage can be synthesized in each PWM switching period Ts by two adjacent nonzero state vectors (000) and (111) [9,26]. This figure represents the adjacent nonzero state vectors and two zero state vectors distribution in the sector I, where d1 and d2 represent the duty rations of nonzero state vectors, and the zero state vectors are generally distributed with an equal duty ration of d0.…”

Section: Proposed Asvpwm Strategy For Zscc Suppressingmentioning

confidence: 99%

“…In addition, this method is only valid for two parallel PWM convertersand also has poor efficiency and more computation complexty, which is not easy to impliment. Many other research works have proposed an adjusting zero-vector duty ratio of space vector pulse width modulation (SVPWM) strategy [9][10][11], [21][22][23][24][25][26]. Zhao et al have proposed an adjusting zero-vector duty ratio of space vector pulse width modulation (ASVPWM) strategy based voltage oriented control (VOC) using PI quasi-resonant control for ZSCC suppression in two parallel rectifiers [9].…”

Section: Introductionmentioning

confidence: 99%

“…In works [10] and [22][23][24], an adjusting zero-vector duty ratio of ASVPWM based VOC using PI quasi-resonant control to suppress the ZSCC in parallel converters was proposed. Other ZSCC suppression strategies in VOC based on PI controllers have proposed in the literature [25][26].…”

Section: Introductionmentioning

confidence: 99%

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Processor-in-the-Loop implementation of an Adjusting Space Vector Pulse Width Modulation for Suppressing Zero-Sequence Circulating Current in Parallel PWM converters

Chebabhi

HUSIN

Kessal

2022

Preprint

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Grid-connected common DC-bus parallel three-phase PWM converters system is widely used in many power systems due to its advantages, including high reliability, sinusoidal grid currents, lower switching frequency, stable DC-bus voltage, and good flexibility. However, this topology suffers from zero-sequence-circulating-current (ZSCC), which will deteriorate the control performance, distort the grid currents, and increase power losses. In this context, an adjusted space vector pulse width modulation strategy (ASVPWM) based on ZSCC fuzzy logic control loop (ZSCC-FLC) is proposed not only to suppress the ZSCC but also to mitigate its ripples and grid current harmonics, especially the third harmonic and their multiples. The main objective of the proposed ZSCC-FLC based ASVPWM strategy is to enforce the ZSCC to zero with very lower ripples in order to accurately provide the appropriate adjusting variable for the duty rations of zero state vectors of ASVPWM. A processor-in-the-loop (PIL) co-simulation is implemented using embedded hardware on the STM32F407 microcontroller discovery-development-board as an experimental study of the proposed ZSCC-FLC based ASVPWM strategy for parallel three-phase PWM converters under balanced and unbalanced grid voltage. Finally, we quantitatively compare both the proposed ZSCC-FLC based ASVPWM strategy to the ZSCC-PIC. This comparison verifies the superiority and effectiveness of the proposed strategy over the ZSCC-PIC strategy in terms of ZSCC, ripples, and inputs currents harmonics.

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Section: Active and Reactive Power Control Loopsmentioning

confidence: 99%

Section: Pi Control Of the Dc-bus Voltagementioning

confidence: 99%

Section: Proposed Asvpwm Strategy For Zscc Suppressingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Processor-in-the-Loop implementation of an Adjusting Space Vector Pulse Width Modulation for Suppressing Zero-Sequence Circulating Current in Parallel PWM converters

Chebabhi

HUSIN

Kessal

2022

Preprint

View full text Add to dashboard Cite

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Experimental Study of the Parameter Mismatch Effects on the Low Frequency Circulating Currents of Parallel Three Phase Inverters

Liberos,

González-Medina,

Patrao

et al. 2023

Eng

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When converters are connected in parallel, a system with some benefits, including modularity and redundancy, is obtained. However, in these circumstances, circulating currents can appear that produce some adverse effects. In this work, a study of the low-frequency circulating currents that appear in three-phase inverters connected in parallel is performed. The study is focused on the effects produced by the parameter mismatch, namely inductance mismatches, power imbalance, and the use of different pulse with modulation (PWM) techniques. The nature of the circulating current produced by each of these factors were analyzed separately. Both simulation and experimental results are shown, which were obtained using a three-phase 10-kW prototype composed of two 5-kW inverters connected in parallel.

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Circulating Current Control in Interleaved and Parallel Connected Power Converters

Javed,

De Croo,

Vandevelde

et al. 2023

Machines

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This article analyzes circulating current control in single-phase power electronic converters, focusing on two different topologies: interleaved and parallel configurations. The study involves a bridgeless interleaving topology with two boost converters for increased efficiency. A parallel connection is also examined for monitoring line current, circulating currents, and power factor control. The article widely explains all current loops, including Common Mode Circulating Currents (CMCC) in the bridgeless interleaved topology and Differential Mode Circulating Currents (DMCC) in parallel-connected interleaved power converters. The proposed control scheme employs voltage and current control loops for output voltage and line current control and introduces CMCC and DMCC compensators to eliminate all types of circulating currents. An efficient Power Factor Correction (PFC) and output voltage control method is presented in this article. The effectiveness of the proposed schemes is validated through comparisons with modern control systems. The results are verified using Simulink/MATLAB and experimental setups with TI Instruments Piccolo prototypes and C2000 (TMS320F28035 microcontroller MCU) microcontrollers in parallel configurations.

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Circulating current reduction of a grid-connected parallel interleaved converter using energy shaping control

Cited by 4 publications

References 18 publications

Processor-in-the-Loop implementation of an Adjusting Space Vector Pulse Width Modulation for Suppressing Zero-Sequence Circulating Current in Parallel PWM converters

Processor-in-the-Loop implementation of an Adjusting Space Vector Pulse Width Modulation for Suppressing Zero-Sequence Circulating Current in Parallel PWM converters

Experimental Study of the Parameter Mismatch Effects on the Low Frequency Circulating Currents of Parallel Three Phase Inverters

Circulating Current Control in Interleaved and Parallel Connected Power Converters

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