Clamped inductive switching of LDMOST for smart power IC's

Abstract

This paper explores the energy capability of an integrated clamped lateral power MOS transistor. The energy capability is determined by switching the device on an inductive load.Experimental results show that the rating of the transistor in terms of energy has to be given along with the drain voltage applied during transient regime. If the clamp voltage increases, the energy capability decreases. This is explained by the presence of a parasitic NPN transistor in the LDMOS transistor. A specific structure is designed in order to determine the energy capability that would correspond to a purely thermal failure mechanism.

Numerical Study of Energy Capability of Si/SiC LDMOSFETs

“…Inductive load switching. The CIS circuit based upon [12] and the resulting devices' electrical characteristics are demonstrated in Fig. 4.…”

Analysis on the Avalanche Ruggedness of Finger Type and Stripe Type LDMOS Transistor

“…Avalanche ruggedness of above equivalent circuits satisfies equations below [3]. Since E=|V|*I*t, the increase of |V| (=absolute value of inductor voltage) leads to decreasing time (t) in the same energy (E) and same inductance (L), that is, the value of dI/dt increases as in Eq.(3).…”