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Thermal failure of 65 V-rated SMARTMOS power devices is analyzed. Failure time measurements in the l ms range correlate with a 3D analytical model. The failure mechanism is shown to be purely thermal, not electrical. The RESURF LDMOS and updrain TMOS devices have equal energy capability per unit area. The low specific on-resistance of the LDMOS (1.6 mCl-cm2) gives it a significant advantage over the updrain TMOS (2.3 m0-cm2) for many automotive applications.

This paper explores the energy capability of an integrated clamped lateral power MOS transistor. The energy capability is determined by switching the device on an inductive load.Experimental results show that the rating of the transistor in terms of energy has to be given along with the drain voltage applied during transient regime. If the clamp voltage increases, the energy capability decreases. This is explained by the presence of a parasitic NPN transistor in the LDMOS transistor. A specific structure is designed in order to determine the energy capability that would correspond to a purely thermal failure mechanism.

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