Clear-performance of linear DEPFET devices

Sandow, C.; Andricek, L.; Fischer, P.; Kohrs, Robert; Krüger, H.; Lütz, G.; Guenther, J.; Reuen, L.; Richter, R.; Strüder, L.; Treis, J.; Trimpl, M.; Wermes, N.

doi:10.1016/j.nima.2006.05.267

Cited by 21 publications

(14 citation statements)

References 7 publications

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“…[10] show that pixel designs similar to the one used in the setup cannot be cleared completely. Hence, additional reset noise has to be considered for the matrix.…”

Section: Total Noisementioning

confidence: 99%

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Performance of a DEPFET pixel system for particle detection

Trimpl

Andricek

Fischer³

et al. 2006

Nuclear Instruments and Methods in Physics Research Section A:

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“…[10] show that pixel designs similar to the one used in the setup cannot be cleared completely. Hence, additional reset noise has to be considered for the matrix.…”

Section: Total Noisementioning

confidence: 99%

“…Hence, additional reset noise has to be considered for the matrix. However, complete clear has been demonstrated for other pixel designs options [10] which will be preferred in future setups. The total noise figure can further be improved by using DEPFET sensors with a higher internal gain g q .…”

Section: Total Noisementioning

confidence: 99%

Performance of a DEPFET pixel system for particle detection

Trimpl

Andricek

Fischer³

et al. 2006

Nuclear Instruments and Methods in Physics Research Section A:

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“…The DEPFET matrix is read out by selecting one row at a time and reading current signals of the columns in parallel. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique [2]: the ''Drain Current Digitizers'' (DCDs), which digitize the drain currents from a row of pixels [3]; and the ''SWITCHERs'', which select and clear the pixels rowwise to send the currents to the DCDs [4,5]; and the ''Data Handling Processors'' (DHPs) are used to reduce the data rates of the DCDs by zero-suppression and readout triggered data only [6]. While the SWITCHERs are located along the side of the DEPFET sensor, DCDs and DHPs are located at the end of the sensor.…”

Section: Introductionmentioning

confidence: 99%

Prototype of a gigabit data transmitter in 65nm CMOS for DEPFET pixel detectors at Belle-II

Kishishita

Krüger

Hemperek

et al. 2013

Nuclear Instruments and Methods in Physics Research Section A:

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a b s t r a c tThis paper describes the recent development of a gigabit data transmitter for the Belle-II pixel detector (PXD). The PXD is an innermost detector currently under development for the upgraded KEK-B factory in Japan. The PXD consists of two layers of DEPFET sensor modules located at 1.8 and 2.2 cm radii. Each module is equipped with three different ASIC types mounted on the detector substrate with a flip-chip technique: (a) SWITCHER for generating steering signals for the DEPFET sensors, (b) DCD for digitizing the signal currents, and (c) DHP for performing data processing and sending the data off the module to the back-end data handling hybrid via $ 40 cm Kapton flex and 12-15 m twisted pair (TWP) cables. To meet the requirements of the PXD data transmission, a prototype of the DHP data transmitter has been developed in a 65-nm standard CMOS technology. The transmitter test chip consists of current-mode logic (CML) drivers and a phase-locked loop (PLL) which generates a clock signal for a 1.6 Gbit/s output data stream from an 80 cm reference clock. A programmable pre-emphasis circuit is also implemented in the CML driver to compensate signal losses in the long cable by shaping the transmitted pulse response. The jitter performance was measured as 25 ps (1s distribution) by connecting the chip with 38 cm flex and 10 m TWP cables.

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“…Another clear pulse follows to the selected row and the cell is sampled again for pedestal readout. It has been shown [9] that the clear process is complete, i.e. all electrons are emptied out of the internal gate, with not too large clear voltage differences (ΔV on/off ≈ 5-7 V) and a constant and fixed clear-gate voltage around 0 V. With complete clearing the statistical fluctuations in the number of electrons in the internal gate are absent as always the same (empty) level of signal charges in the internal gate is reached.…”

Section: Operation Of Depfet Matricesmentioning

confidence: 98%

“…all electrons are emptied out of the internal gate, with not too large clear voltage differences (ΔV on/off ≈ 5-7 V) and a constant and fixed clear-gate voltage around 0 V. With complete clearing the statistical fluctuations in the number of electrons in the internal gate are absent as always the same (empty) level of signal charges in the internal gate is reached. Complete clearing can be achieved by short clear pulses (∼10 ns) [9]. A photograph of the DEPFET-Matrix hybrid assembly is shown in Fig.…”

Section: Operation Of Depfet Matricesmentioning

confidence: 99%

Performance of a DEPFET Prototype Module for the ILC Vertex Detector

Reuen¹,

Kohrs²,

Velthuis³

et al.

IEEE Nuclear Science Symposium Conference Record, 2005

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For the detection of secondary vertices of long lived bottom and charm quarks at the proposed International Linear Collider (ILC) a DEPFET pixel detector is one of the technologically favored options. DEPFET pixel sensors, in which the amplifying transistor structure is contained in the pixel cell itself on a fully depleted bulk, are unique devices in terms of their large signal and low noise capability and their obtainable spatial resolution with very thin detectors. DEPFET pixel prototype modules with close to ILC specifications have been tested in the laboratory and, for the first time, in a 6 GeV electron test beam. The different noise sources have been calculated and compared with the measured value of ENC ≈ 225 e − for the entire system.

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Clear-performance of linear DEPFET devices

Cited by 21 publications

References 7 publications

Performance of a DEPFET pixel system for particle detection

Performance of a DEPFET pixel system for particle detection

Prototype of a gigabit data transmitter in 65nm CMOS for DEPFET pixel detectors at Belle-II

Performance of a DEPFET Prototype Module for the ILC Vertex Detector

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