Clip 4 parallel processing system

Fountain, T. J.; Goetcherian, V.

doi:10.1049/ip-e.1980.0045

Cited by 6 publications

(5 citation statements)

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“…The second generation comprises systems such as the ICL DAP [26], the Goodyear MPP [2] and the CLIP4 system [14] which have evolved to complete processing systems with dedicated operating systems and languages and extended the application spectrum to high-speed scienti®c computation.…”

Section: Discussionmentioning

confidence: 99%

Architectural Issues on Vision-Based Automatic Vehicle Guidance: The Experience of the ARGO Project

2000

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Section: Discussionmentioning

confidence: 99%

Architectural Issues on Vision-Based Automatic Vehicle Guidance: The Experience of the ARGO Project

2000

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“…From (13) and (14) we get g n−i (p n−i ) = g n−i (q n−i ). Thus p n−i = q n−i since g n−i is a bijective mapping.…”

Section: Appendix Proof Of Propertymentioning

confidence: 99%

“…In a reconfigurable network each node has a bounded degree of connectivity but the network diameter is restricted by allowing the network to reconfigure itself into different configurations. Examples of reconfigurable multiprocessor systems include the Polymorphic Torus [23], [24], Gated-Connection Network (GCN) [18], [36], CLIP7 [13], PAPIA2 [1], Reconfigurable Bus Architecture (RBA) [26], and the Reconfigurable Mesh Architecture (RMA) [27]. A considerable amount of research in recent times has been devoted in attempts to show that these reconfigurable systems are well-suited for computer vision problems.…”

Section: Introductionmentioning

confidence: 99%

Parallel computer vision on a reconfigurable multiprocessor network

Ehandarkar

Arabnia

1997

IEEE Trans. Parallel Distrib. Syst.

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A novel reconfigurable architecture based on a multiring multiprocessor network is described. The reconfigurability of the architecture is shown to result in a low network diameter and also a low degree of connectivity for each node in the network. The mathematical properties of the network topology and the hardware for the reconfiguration switch are described. Primitive parallel operations on the network topology are described and analyzed. The architecture is shown to contain 2D mesh topologies of varying sizes and also a single one-factor of the Boolean hypercube in any given configuration. A large class of algorithms for the 2D mesh and the Boolean n-cube are shown to map efficiently on the proposed architecture without loss of performance. The architecture is shown to be well suited for a number of problems in low-and intermediate-level computer vision such as the FFT, edge detection, template matching, and the Hough transform. Timing results for typical low-and intermediate-level vision algorithms on a transputerbased prototype are presented.

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“…Differentiating f, as defined in equatiomi 1 with respect to time, we obtain ft = -tLfx -v. f (3) where f denotes the temporal derivative of f. Filtering both sides of equation 3 with g we obtain: g®ft = -u.gØf -v.g®f (4) The derivative operation is commutative with respect to convolution so the above equation can be rewritten as: = -u.g®f-v.g®f (5) This operation eliminates the need to calculate the spatial derivative of the image function. Similarly, we choose a second filter, h(x, y), that is linearly independent of g(x,y) and get h ® ft = -u .…”

Section: Theorymentioning

confidence: 99%

“…SIMD processors are fully parallel and use a two (limensional array of simple processing elements each having a direct correspondence with the pixels of the image. Examples include the CLIP-4 and CLIP7 [4,5,6], DAP [16], MPP [3], AIS-5000 [19] and the CM [8]. MIMD systems use an array of processors that each operate on a segment of the image.…”

Section: Introductionmentioning

confidence: 99%

<title>Hardware system for computing image velocity in real time</title>

et al. 1992

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A multi-purpose hardware system for processing images at video rates is described. ISHTAR (Image Sequence Hardware for Temporal Analysis in Realtime) uses 18 TI TMS32Oc4O (c40) DSP's to process input from a CCD camera or VCR source. The hardware architecture consists of a pipeline of nine processor boards, each with two c40 processors, the whole system being syrichronised by the vertical sync of the input device. This enables the calculation of a number of two dimensional convolutions to be achieved at video frame rates with a delay between the input and the output dictated by the length of the pipeline. The system is fully reconfigurable in software and partially reconfigurable in hardware so that many different types of image processing algorithms can be implemented. The specific application of a generalised gradient model to measure image motion is described, outlining the particular program structure dictated by the hardware design. The SUN 4 host has access to each processor and has the ability to change parameters and program control while the system is running. In this way active control feedback loops can be employed, particularly when the motion of the camera is under the host control, forming an active vision system. Simulations using real image sequences are presented.

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Clip 4 parallel processing system

Cited by 6 publications

References 0 publications

Architectural Issues on Vision-Based Automatic Vehicle Guidance: The Experience of the ARGO Project

Architectural Issues on Vision-Based Automatic Vehicle Guidance: The Experience of the ARGO Project

Parallel computer vision on a reconfigurable multiprocessor network

<title>Hardware system for computing image velocity in real time</title>

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