Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC

Ravezzi, L.; Partovi, H.

doi:10.1109/jssc.2015.2402222

Cited by 10 publications

(6 citation statements)

References 14 publications

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“…Clock gating, in which clock switching to sequential elements is restrained to reduce unnecessary dynamic power, is considered one of the most widely adopted low-power techniques. Clock gating can include fine-grained to coarse clock gating by disabling a small group of registers, a cluster of registers in a module, or an entire functional unit [16]. The Rx circuit reset pin (RS) can easily shut off certain portions of the CDN to perform clock gating.…”

Section: A Receiver (Current-to-voltage Converter) Circuit Designmentioning

confidence: 99%

HCDN: Hybrid-Mode Clock Distribution Networks

Islam

Guthaus

2019

IEEE Trans. Circuits Syst. I

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We propose a new hybrid clock distribution scheme that uses global current-mode (CM) and local voltage-mode (VM) clocking to distribute a high-performance clock signal with reduced power consumption. In order to enable hybrid clocking, we propose two new current-to-voltage converters. The converters are simple current receiver circuits based on amplifier and current-mirror circuits. The global clocking is bufferless and relies on current rather than voltage, which reduces the jitter. The local VM network improves compatibility with traditional CMOS logic. The hybrid clock distribution network exhibits 29% lower average power and 54% lower jitter-induced skew in a symmetric network compared to traditional VM clocks. To use hybrid clocking efficiently, we present a methodology to identify the optimal cluster size and the number of required receiver circuits, which we demonstrate using the ISPD 2009, ISPD 2010, and ISCAS89 testbench networks. At 1-2GHz clock frequency, the proposed methodology uses up to 45% and 42% lower power compared to a synthesized buffered VM scheme using ISPD 2009 and ISPD 2010 testbenches, respectively. In addition, the proposed hybrid clocking scheme saves up to 50% and 59% of power compared to a buffered scheme using the ISCAS89 benchmark circuit at 1GHz and 2GHz clock frequency, respectively.

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Section: A Receiver (Current-to-voltage Converter) Circuit Designmentioning

confidence: 99%

HCDN: Hybrid-Mode Clock Distribution Networks

Islam

Guthaus

2019

IEEE Trans. Circuits Syst. I

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“…The former can be modelled as a Gaussian distribution [19]. The latter, however, depends on several factors and can be random with arbitrary distribution [20]. The analysis in this section assumes that the jitter has a Gaussian distribution.…”

Section: Markov Chain Model For Gaussian Distributed Random Jittermentioning

confidence: 99%

Settling time of mesochronous clock re-timing circuits in the presence of timing jitter

Kadayinti

Budkuley

Sharma

2017

2017 IEEE International Symposium on Circuits and Systems (ISCAS)

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It is well known that timing jitter can degrade the bit error rate (BER) of receivers that recover clock information from the input data. However, timing jitter can also result in an indefinite increase in the settling time of clock recovery circuits at the receivers, particularly in low swing mesochronous systems. Mesochronous clock retiming circuits are required in repeaterless low swing on-chip interconnects in order to sample the low swing data at the center of the eye. This paper discusses the settling time of these circuits. First, a discussion on how timing jitter can result in large increase in the settling time of the clock recovery circuit is presented. Next, the circuit is modeled as a Markov chain with absorbing states. Here, the mean time of absorption of the Markov chain, which represents the mean settling time of the circuit, is determined. The model is validated by using behavioural simulations of the circuit, the results of which match well with the model predictions. The modelling is applied to study the effect of different types of jitter, like data dependent jitter of 1 bit and 2 bits, random jitter and random jitter along with 1 bit data dependent jitter. Finally, a few techniques of reducing the settling time are presented and their efficacy is confirmed with circuit simulations.

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“…随着高性能微处理器向着核心数量越来越多的方向发展, 结合各种拓扑结构优点的混合型 CDN 开始流行. 该类 CDN 一般是由全局 H 树型 (global H-driven-tree) 时钟网络驱动局部的时钟网络, 局部时钟网络一般为 Mesh 或二叉树或鱼骨状 (fishbone), 如文献 [10] 提到的 8 核 ARM 处理器和文献 [11]…”

Section: 结构描述unclassified

容工艺偏差的低偏斜层次化时钟网络设计

Wang¹,

Ke²

2015

Sci. Sin.-Inf.

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中国科学 : 信息科学第 45 卷第 4 期图 1 (a) CTS 结构; (b) 传统 clock Mesh 结构 Figure 1 (a) CTS structure; (b) conventional clock Mesh structure Clock Mesh 则是通过短接在一起的时钟布线网格来实现时钟信号的接近零偏差的传播, 如图 1(b) 所示. 其将每一个 Mesh driver 的输出短接在一起, 使得时钟信号能够非常快的, 并且几乎同时到达每个受驱动节点. 高性能微处理器一般采取这种方式. 但 clock Mesh 的时钟功耗较大 [5] , 占用的布线资源较多, 且根据图 1(b), 在 Mesh 网格之后还存在一定级数的时钟驱动缓冲器, 同样难以做到真正的零偏斜的传播时钟信号.

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Clock and Synchronization Networks for a 3 GHz 64 Bit ARMv8 8-Core SoC

Cited by 10 publications

References 14 publications

HCDN: Hybrid-Mode Clock Distribution Networks

HCDN: Hybrid-Mode Clock Distribution Networks

Settling time of mesochronous clock re-timing circuits in the presence of timing jitter

容工艺偏差的低偏斜层次化时钟网络设计

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