HCDN: Hybrid-Mode Clock Distribution Networks

Abstract

We propose a new hybrid clock distribution scheme that uses global current-mode (CM) and local voltage-mode (VM) clocking to distribute a high-performance clock signal with reduced power consumption. In order to enable hybrid clocking, we propose two new current-to-voltage converters. The converters are simple current receiver circuits based on amplifier and current-mirror circuits. The global clocking is bufferless and relies on current rather than voltage, which reduces the jitter. The local VM network improves compatibility with traditional CMOS logic. The hybrid clock distribution network exhibits 29% lower average power and 54% lower jitter-induced skew in a symmetric network compared to traditional VM clocks. To use hybrid clocking efficiently, we present a methodology to identify the optimal cluster size and the number of required receiver circuits, which we demonstrate using the ISPD 2009, ISPD 2010, and ISCAS89 testbench networks. At 1-2GHz clock frequency, the proposed methodology uses up to 45% and 42% lower power compared to a synthesized buffered VM scheme using ISPD 2009 and ISPD 2010 testbenches, respectively. In addition, the proposed hybrid clocking scheme saves up to 50% and 59% of power compared to a buffered scheme using the ISCAS89 benchmark circuit at 1GHz and 2GHz clock frequency, respectively.

Early Stage DRC Prediction Using Ensemble Machine Learning Algorithms

“…Machine learning has widespread applications, including text sentiment classification [12], [13], [14], [15], [16], [17], natural language processing [18], [19], [20], and sarcasm identification [21], while, in recent years, researchers have shown a tremendous interest in machine learning applications in IC physical design tools [2], [5], [6], [7], [22], [23], [24], [25], [26], [27], [28], [29], [30], [31], [32], [33], [34]. Static timing analysis (STA) is a key step in the IC design flow, and machine learning algorithms can play a key role in estimating delay.…”

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“…K-mean has been used for sink points clustering by researchers [68] and branching points identification by researchers [69]. In this paper, the algorithm has been extended to enable global CTS for a hierarchical design that is obstacle dominant at top level.…”

“…Even though dynamic de-skew circuit can produce both low skew and OCV induced jitters, to design and validate a dynamic circuit, it requires high skillset and efforts that are not trivial. Similar limitations happen to other complex topology solutions such as differential signal circuitry [19], global resonant H-tree [20], current-mode [68], and hybrid radio frequency (RF)/Metal clock routing [21] [22]. In the new business environment, the market prefers a highly integrated but low power SoC with fast design productivity and low development cost as listed in challenges and possible solution Section of ITRS 2.0 2015 [23].…”

“…It is a "chicken and egg" situation as accurate voltage drop profile will not be available without clock trees and voltage drop profile will change whenever clock tree changes. Researchers [68] have recommended global current-mode and local voltage-mode clock distribution networks to reduce power consumption and jitter effects. However, it is not practical to implement and validate current-mode circuitries for a complex SoC which has hundreds of clock domains with each have from thousands to millions of sink points.…”

Design of a 1.5 GHz Low jitter DCO Ring in 28 nm CMOS Process

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