Clock gating methodologies and tools: a survey

Abstract

Clock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits. Although it is a mature technique, theoretical work and tools for its application are still evolving and considered a matter of ongoing research, due to its significant effect in the overall power of the designs under study. This paper introduces a detailed review of the spectrum of CG approaches, theoretical and practical, from an architectural and register transfer level to synthesis, place and route, and testing issues. Furthermore, tools availability, limitations, and requirements concerning CG are examined for each design flow step. Conclusively, an evaluation of the presented techniques and literature is provided, estimating their usefulness and identifying areas for future research, exploration, and automation. Figure 3. Basic CG structure. A clock input and a CG function provide the Clk and En signals to the ICG (integrated CG), which generates the gated clock used by the registers. CLOCK GATING METHODOLOGIES AND TOOLS: A SURVEY 801consumption is getting higher on the priorities and risks, during specifications and requirements definition, meaning that power saving exploration needs to be exhaustive. Thus, the research space and tool development for CG applications and optimizations remain as relevant as ever. 816G. POUIKLIS AND G. CH. SIRAKOULIS

Trivium hardware implementations for power reduction

“…In ASIC implementation, power results for a Trivium in a 130-nm CMOS technology were described in [12,13] where 227 and 175 μW of average power were obtained at 10 MHz. In [15], power consumption in a radix-16 Trivium optimized for passively powered devices was reduced by applying clock gating [16] and sleep mode logic as a means of reducing the effective clock frequency. In [15], power consumption in a radix-16 Trivium optimized for passively powered devices was reduced by applying clock gating [16] and sleep mode logic as a means of reducing the effective clock frequency.…”

“…Another set of power results for a Trivium in 130 and 350 nm was shown in [14], where 337 and 641 μW were obtained at 5 MHz. In [15], power consumption in a radix-16 Trivium optimized for passively powered devices was reduced by applying clock gating [16] and sleep mode logic as a means of reducing the effective clock frequency. Twenty-two clock cycles were needed to generate a 16-bit key stream, and source current values below 1 μA at 100 KHz and 1.5 V were obtained in 350-nm technology.…”

Ανάπτυξη Ψηφιακών Ηλεκτρονικών Χαμηλής Ισχύος, Σε Ολοκληρωμένα Κυκλώματα Μικτού Σήματος Για Διαστημικές Εφαρμογές

“…Επιπρόσθετα από την έρευνα τρόπων µείωσης της κατανάλωσης ισχύος, προέκυψαν θεωρητικά ερευνητικά αποτελέσµατα τα οποία δηµοσιεύτηκαν σε δύο εργασίες. Η πρώτη σχετίζεται µε τεχνικές clock gating [33], ενώ η δεύτερη µε δυναµική ρύθµιση της τάσης τροφοδοσίας για εφαρµογές µε απαιτήσεις αντοχής σε φαινόµενα SEU [59].…”

“…∆ηλαδή το µειονέκτηµα της απαραίτητα υψηλής τάσης για λόγους SEU, το χρησιµοποιούµε για να καταστήσουµε εφικτές µεθοδολογίες χαµηλής κατανάλωσης ενέργειας. Αυτές οι τεχνικές σε συνδυασµό µε τις layout τεχνικές που αναλύθηκαν στο τρίτο κεφάλαιο, καθιστούν αυτό το κύκλωµα ανθεκτικό σε ακτινοβολία µε µειωµένη κατανάλωση ισχύος [33].…”

“…Αυτή η επιλογή γίνεται από έξι πολυπλέκτες (όσοι και οι όροι του πολυωνύµου-γεννήτριας) και εξαρτάται από τις τιµές των εισόδων CRC-shiftout και Tx-busy. Το ρολόι χρονισµού αυτού του κυκλώµατος αποκόπτεται µε clock-gating [33] κατά τα διαστήµατα που είναι ανενεργό. Σχήµα 6.5: Μπλοκ διάγραµµα του κυκλώµατος CRC.…”