Network applications are becoming increasingly popular in the embedded systems domain requiring high performance, which leads to high energy consumption. In networks is observed that due to their inherent dynamic nature the dynamic memory subsystem is a main contributor to the overall energy consumption and performance. This paper presents a new systematic methodology, generating performance-energy trade-offs by implementing Dynamic Data Types (DDTs), targeting network applications. The proposed methodology consists of: (i) the application-level DDT exploration, (ii) the network-level DDT exploration and (iii) the Pareto-level DDT exploration. The methodology, supported by an automated tool, offers the designer a set of optimal dynamic data type design solutions. The effectiveness of the proposed methodology is tested on four representative real-life case studies. By applying the second step, it is proved that energy savings up to 80% and performance improvement up to 22% (compared to the original implementations of the benchmarks) can be achieved. Additional energy and performance gains can be achieved and a wide range of possible trade-offs among our Pareto-optimal design choices are obtained, by applying the third step. We achieved up to 93% reduction in energy consumption and up to 48% increase in performance. . IntroductionIn the last years, there is a trend toward networks and network applications implemented with the use of embedded consumer devices. The complexity of modern wired and wireless networks combined with the increased interaction with the environment (e.g. in wireless networks) has increased the dynamism of the data access pattern.The dynamism of network applications depends on various factors. One of them is the network traffic. Depending on that, the behavior of functions, as well as the number of times they are executed, differ. The amount of stored data, needed for these functions, varies as well. Thus, dynamically adjustable storage size is a necessity, allowing for freeing of memory when it is no longer needed. Moreover, a static memory allocation at compile time is not an option in the case of most modern network applications, because they do not have a static data access behavior, but rather a dynamic one. This fact means that a static memory allocation at compile time is not efficient at all, because the worst case situation has to be assumed in the beginning and implemented for the whole execution time. Therefore, dynamic memory allocation and management is required (especially in embedded systems). This leads to an increased reliance on Dynamic Data Types (DDTs from now on), the structures, which allow data to be dynamically allocated and deallocated at run-time and provide an easy way for the designer to connect, access and process data [17]. DDTs (with the most common examples being the single and doubly linked lists) can efficiently cope with the variations of runtime needs (e.g. network traffic, user interaction) and the massive amounts of transferred and stored data.Ine...

Clock gating (CG) is a widely used design method for reducing the dynamic power consumption in digital circuits. Although it is a mature technique, theoretical work and tools for its application are still evolving and considered a matter of ongoing research, due to its significant effect in the overall power of the designs under study. This paper introduces a detailed review of the spectrum of CG approaches, theoretical and practical, from an architectural and register transfer level to synthesis, place and route, and testing issues. Furthermore, tools availability, limitations, and requirements concerning CG are examined for each design flow step. Conclusively, an evaluation of the presented techniques and literature is provided, estimating their usefulness and identifying areas for future research, exploration, and automation. Figure 3. Basic CG structure. A clock input and a CG function provide the Clk and En signals to the ICG (integrated CG), which generates the gated clock used by the registers. CLOCK GATING METHODOLOGIES AND TOOLS: A SURVEY 801consumption is getting higher on the priorities and risks, during specifications and requirements definition, meaning that power saving exploration needs to be exhaustive. Thus, the research space and tool development for CG applications and optimizations remain as relevant as ever. 816G. POUIKLIS AND G. CH. SIRAKOULIS

No abstract

No abstract

Abstract. This paper presents a new perspective to the design of wireless networks using the proposed dynamic data type refinement methodology. In the forthcoming years, new portable devices will execute wireless network applications with extensive computational demands (2 -30 GOPS) with low energy consumption demands (0.3 -2 Watts). Nowadays, in such dynamic applications the dynamic memory subsystem is one of the main sources of energy consumption and it can heavily affect the performance of the whole system, if it is not properly managed. The main objective is to arrive at energy efficient realizations of the dominant dynamic data types of this dynamic memory subsystem. The simulation results in real case studies show that our methodology reduces energy consumption 50% on average.