Clock Mesh Network Design with Through-Silicon Vias in 3D Integrated Circuits

Abstract

Many methodologies for clock mesh networks have been introduced for two‐dimensional integrated circuit clock distribution networks, such as methods to reduce the total wirelength for power consumption and to reduce the clock skew variation through consideration of buffer placement and sizing. In this paper, we present a methodology for clock mesh to reduce both the clock skew and the total wirelength in three‐dimensional integrated circuits. To reduce the total wirelength, we construct a smaller mesh size on a die where the clock source is not directly connected. We also insert through‐silicon vias (TSVs) to distribute the clock signal using an effective clock TSV insertion algorithm, which can reduce the total wirelength on each die. The results of our proposed methods show that the total wirelength was reduced by 12.2%, the clock skew by 16.11%, and the clock skew variation by 11.74%, on average. These advantages are possible through increasing the buffer area by 2.49% on the benchmark circuits.

Clock skew reduction for stacked chips using multiple source buffers

“…Navid et al [7] have proposed a 3D symmetrical centroid tree CDN (SCT CDN). Chao et al [9] have proposed a 3D clock mesh with local mesh sizing. Thermal-aware clock tree optimization [10] and the synthesis considering thermal coupling [11] have been presented.…”

“…Several researchers have developed effective methods for the clock distribution network (CDN) of 3D ICs [2][3][4][5][6][7][8][9][10][11][12][13][14][15][16] such as 3D clock tree synthesis. Several techniques have been proposed for CDN physical structures.…”