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We propose a model for coupling that considers substrate contacts between through silicon vias (TSVs) in bulk-CMOS technologies. The proposed model is compact but has reasonable accuracy for the dense substrate contacts in largescale three dimensional integrated circuits (3D ICs). We describe the modeling for substrate contacts with the equivalent electrical circuit, discuss the impact of substrate contacts on the electrical parasitic parameters, and clarify the effect of substrate contacts on reducing crosstalk noise and increasing delay. Results of analysis show that if substrate contacts are not considered, crosstalk noise becomes the overestimate of 5 to 700 times and delay becomes the underestimate of 1.4 to 2.4 times.

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In this paper, we propose a method to reduce clock skew among stacked chips by a clock distribution network with multiple source buffers (MSB CDN). The propagation delays to all chips that need a clock signal are tuned only in the chip with a clock source. The adjustment is done in accordance with the size and number of buffers. Receivers in the same conditions are placed on the other chips. The output signals of the receivers are subjected to waveform shaping. In this way, the delays and slews are unified. The proposed method has the advantage that all the chips except for the chip with a clock source can be designed by using a conventional method such as buffered clock tree synthesis (CTS). The experimental results demonstrate that the proposed method can reduce clock skew.