Impact of on-chip interconnects on vertical signal propagation in 3D ICs

Niioka, Nanako; Watanabe, Masayuki; Karel, Rosely; Kobayashi, T.; Imai, Masayuki; Fukase, Masa-aki; Kurokawa, Atsushi

doi:10.1109/apccas.2014.7032854

Cited by 4 publications

(1 citation statement)

References 17 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Fig. 12 shows the equivalent circuit, which appended the model of coarse-grained substrate contacts [20] to the model in [18,19]. Table I lists the physical and material parameters used in our analysis.…”

Section: Resultsmentioning

confidence: 99%

Clock skew reduction for stacked chips using multiple source buffers

Niioka

Imai

Fukase

et al. 2015

2015 15th International Symposium on Communications and Information Technologies (ISCIT)

Self Cite

View full text Add to dashboard Cite

In this paper, we propose a method to reduce clock skew among stacked chips by a clock distribution network with multiple source buffers (MSB CDN). The propagation delays to all chips that need a clock signal are tuned only in the chip with a clock source. The adjustment is done in accordance with the size and number of buffers. Receivers in the same conditions are placed on the other chips. The output signals of the receivers are subjected to waveform shaping. In this way, the delays and slews are unified. The proposed method has the advantage that all the chips except for the chip with a clock source can be designed by using a conventional method such as buffered clock tree synthesis (CTS). The experimental results demonstrate that the proposed method can reduce clock skew.

show abstract

Section: Resultsmentioning

confidence: 99%