Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion

Abstract

Under the assumption that clock can be inputted to each register at an arbitrary timing, the minimum feasible clock period can be determined if delays between registers are given. This minimum feasible clock period might be reduced if delays between some registers are increased by delay insertion. In this paper, we propose a delay insertion algorithm to reduce the minimum clock period. First, the proposed algorithm determines a clock schedule ignoring some constraints. Second, the algorithm inserts delays to recover ignored constraints according to the delay-slack and delay-demand of the obtained clock schedule. We show that the proposed algorithm achieves the minimum clock period by delay insertion if the delay of each element in the circuit is unique. Experiments show that the amount of inserting delay and computational time are smaller than the conventional algorithm.

A Low Area Overhead Design Method for High-Performance General-Synchronous Circuits with Speculative Execution

“…The clock scheduling [6], [7], the delay insertion [8], [9] and the introduction of speculative execution [1] are adopted to the input circuit G and the output circuit is generated. The generated circuit works correctly when it is oper- ated with the clock period 6.…”

“…and the minimum delay of a primitive computation between the appropriate pair of flip-flops relaxes to find a feasible clock scheduling and leads to the clock period minimization [9]. The minimum delay is able to increase by some techniques such as inserting buffers or replacing logic cells to smaller ones.…”

“…However, it is difficult to equalize the maximum delay of all paths in a circuit, and the delay difference remains in optimized circuits. Clock period minimization methods [6]- [9] on general-synchronous circuit completely reduce the waiting time of the former one and achieve higher performance than C-circuits. General-synchronous circuit (hereinafter, we simply call this as "circuit") is a synchronous circuit in which the clock signals have the same period but the timing they ticks is different.…”

“…The clock scheduling [6], [7] finds a feasible clock scheduling to assign an appropriate delay to each path. The delay insertion [8], [9] expands the feasibility of the clock scheduling by increasing the minimum delay of paths and achieves the minimum clock period of a circuit assuming fixed-latency.…”

The FPGA based emulation of complex SoC for ADAS market on ZeBu-Server

“…In addition, the clock signal tends to be highly loaded. To distribute the clock and control the clock skew, one needs to construct a clock network often a clock tree) with clock buffers [9], [10] and [11].…”