Clock period minimization of semi-synchronous circuits by gate-level delay insertion

Abstract

A semi-synchronous circuit is a circuit in which every register is ticked by a clock periodically, but not necessarily simultaneously. A feature of semi-synchronous circuits is that the minimum delay between registers may be critical with respect to the clock period of the circuit. In this paper, we discuss a delay insertion method which makes such a semi-synchronous circuit faster. The maximum delay-to-register ratio of the cycles on the circuit gives a lower bound of the clock period. We show that this bound is achieved in the semi-synchronous framework by the proposed gate-level delay insertion method on the assumption that the delay of each element on the circuit is unique.

Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization

“…Step 1 : Determine T L (G) from the constraint graph consisting of Z-edges ( [10]). If T S (G) = T L (G), a critical-cycle which consists of only Z-edges exists in the constraint graph [9]. So, if T S (G) = T L (G), the proposed method cannot improve the minimum clock period in g-frame since no target register exists on the critical-cycle.…”

“…Since the minimum clock Proof. If T S (G) = T L (G), a critical-cycle which consists of only Z-edges exists in H(G) [9]. Since a critical-cycle which consists of only Z-edges contains no target register, the critical-cycle is a maximal critical-cycle.…”

“…As logic circuit modification methods that improve the performance in g-frame, delay insertion methods [9]- [11], a gate sizing method [12], a multi-clock cycle path method [13], and a register relocation method [14] are proposed.…”

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework

“…Therefore, the optimization of circuit synthesis that takes g-frame into account must be investigated. In this paper, we focus on delay insertion methods [6]- [9]. Even though we do not consider the detailed delay insertion methods, the delay insertion will be realized by replacing a large module with a small module synthesized under looser delay constraints, by using smaller transistors and narrower wires, and by deleting buffers from long interconnects, as well as by inserting buffers to short interconnects.…”

“…In [6], a delay insertion method that minimizes the clock period was proposed. Since the amount of an inserted delay is iteratively determined by searching the whole circuit, the method takes too much computation time.…”