Clocked comparator for high-speed applications in 65nm technology

Abbas, Mohamed; Furukawa, Yasuo; Komatsu, Setsuko; Takahiro, J Yamaguchi; Asada, Kunihiro

doi:10.1109/asscc.2010.5716609

Cited by 63 publications

(66 citation statements)

References 10 publications

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“…These results indicate that the input referred noise is reduced as ∆STR increased, and the input referred noise of the proposed comparator is around 320µV when it operates at 1GHz with ∆STR in 61ps and at 1.5GHz with ∆STR in 79ps. Table I illustrates a benchmark of the state-of-the-art comparator architectures, comparing the current design with relevant works from [2], [3] and [5], showing the enhanced results of the proposed architecture. The measured power consumption of the proposed comparator is larger than [2] which mainly due to the rise of supply voltage in the adopted technology.…”

Section: Measurement Resultsmentioning

confidence: 98%

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

Chan

Zhu

Chio

et al. 2011

IEEE Asian Solid-State Circuits Conference 2011

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This paper presents a reconfigurable, low offset, low noise and high speed dynamic clocked-comparator for medium to high resolution Analog to Digital Converters (ADCs). The proposed comparator reduces the input referred noise by half and shows a better output driving capability when compared with the previous work. The offset, noise and power consumption can be controlled by a clock delay which allows simple reconfiguration. Moreover, the proposed offset calibration technique improves the offset voltage from 11.6mV to 533µV at 1 sigma. A prototype of the comparator is implemented in 90nm 1P8M CMOS with experimental results showing 320µV input referred noise at 1.5GHz with 1.2V supply.

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Section: Measurement Resultsmentioning

confidence: 98%

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

Chan

Zhu

Chio

et al. 2011

IEEE Asian Solid-State Circuits Conference 2011

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show abstract

“…In order to achieve more settling time, a high speed comparator is introduced in the SHA-less structure. Many methods have been developed to increase the speed of comparator [8,9]. Fig.…”

Section: High Speed Comparatorsmentioning

confidence: 99%

“…Fig. 4 shows the schematic of a doubletail comparator with low power cost in reference [8]. The comparator introduces a preamplifier and the output of the preamplifier is directly connected to the next latching nodes to promote regeneration.…”

Section: High Speed Comparatorsmentioning

confidence: 99%

A 12 bit 120 MS/s SHA-less pipeline ADC with capacitor mismatch error calibration

Zhou

Lin

Huang

et al. 2018

IEICE Electron. Express

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In this paper, a 12-bit pipeline Analog-to-Digital (ADC) in 0.13 µm CMOS process with SHA-less structure is presented. Two kinds of high-speed comparators are proposed to reduce settling time of residue amplifier. Meanwhile, the foreground calibration algorithm can correct the mismatch of capacitors and alleviate the effect of finite gain of residue amplifier for better linearity. A single-to-differential reference voltage buffer which can be easily controlled by the reference voltage outside is also designed in this ADC. Measurement results show that the ADC achieves an spurious-free dynamic range (SFDR) of 83.6 dBc, a signal-to-noise ratio (SNR) of 67.16 dB and a signal-to-noise and distortion ratio (SNDR) of 66.9 dB with 9.95 MHz input signal at 120 MS/s. The integral nonlinearity (INL) and differential nonlinearity (DNL) are within ²0.8 LSB and ²0.25 LSB, respectively.

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“…This ADC uses a dynamic two-stage design, as shown in Fig. 8, 16 which focuses on speed rather than energy e±ciency. The¯rst stage is a voltage ampli¯cation with di®erential inputs V P and , working for the purpose of regeneration.…”

Section: Dynamic Two-stage Comparatormentioning

confidence: 99%

An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

Zhang

Zhu

et al. 2015

J CIRCUIT SYST COMP

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This paper presents an 8-bit con¯gurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates sixphase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under di®erent modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.

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Clocked comparator for high-speed applications in 65nm technology

Cited by 63 publications

References 10 publications

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

A reconfigurable low-noise dynamic comparator with offset calibration in 90nm CMOS

A 12 bit 120 MS/s SHA-less pipeline ADC with capacitor mismatch error calibration

An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

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