An 8-Bit 0.333–2 GS/s Configurable Time-Interleaved SAR ADC in 65-nm CMOS

Abstract

This paper presents an 8-bit con¯gurable time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). By using a mode selection circuit, four modes of sampling rate are provided: Single channel at 333.3 MS/s, 2-channel at 666.7 MS/s, 3-channel at 1 GS/s and 6-channel at 2 GS/s. An on-chip delay-locked loop (DLL) uniformly generates sixphase clock with 20% duty cycle, and the timing errors are reduced to a tolerable range. In low sampling rate modes, the corresponding sampling switches and comparators in the idle sub-ADCs are shut down to save power consumption. Based on the 65-nm CMOS technology, the post-layout simulation results show that at 1.2 V supply, the proposed ADC consumes 8.6, 10.9, 13.1 and 19.9 mW under di®erent modes. With an ENOB of 7.92, 7.34, 7.01 and 6.37 bit, this results in a FOM of 106.6, 100.9, 101.6 and 120.3 fJ/conversion-step respectively.

Design of an X-ray diagnosis system with TIADC

“…Table 1 presents a comparative analysis of the proposed approach with alternative methods ( [14][15][16]). The comparative analysis of experimental results indicates that the performance of the system, which has been enhanced by the methodology introduced in this paper, surpasses the performance of the aforementioned TIADC systems.…”