Closed-loop Built in Self Test for PLL production testing with minimal tester resources

Abstract

Phase Locked Loops (PLLs) are extensively used in modern System on a Chip (SoC) modules for generating timing, clock signal recovery and to provide a timing reference for communication interfaces. Due to their use in crucial and omnipresent applications, PLLs are the only mixed signal components on many otherwise digital blocks. The mixed signal nature makes testing of PLLs complicated as the output test requirements include non-digital parameters such as phase error, lock time, jitter along with the typical frequency locking test. Automatic Test Equipment (ATE) resources needed for these added parameters may require the use of a higher-end ATE for an otherwise digital block, driving up the production test costs. Built in Self Test (BiST) approaches for PLLs need to be carefully designed due to the load-sensitive nature of the internal analog nodes as well as sensitivity of the feedback path to any added delays by the BiST overhead. Our scheme proposes a mixedsignal closed loop complete test solution for a PLL by injecting a BiST signal at non-sensitive internal nodes and observing a low frequency(LF)/DC output in order to perform a pass/fail decision on the PLL. The goal of this scheme is to enable complete production quality at-speed testing of a PLL using minimal ATE resources.

Design of a Fully Integrated VHF CP-PLL Frequency Synthesizer with an All-Digital Defect-Oriented Built-In Self-Test.

“…Next, the BIST circuitry should be more rugged than the IC to guarantee low failure probability. As a good strategy, some BIST designs even attempt to include checker facilities to test the infrastructure itself [12,19]. Finally, the BIST should also interface easily with standard test access mechanisms and must be portable across technology nodes without requiring significant reconfiguration.…”

Frequency-Independent Parametric Built in Test Solution for PLLs with Low Speed Test Resources

“…All the three schemes presented in this prior work use additional circuits in the feedback loop and would result in a phase shift as well as frequency dependence on the input signal as the atspeed signal in the feedback loop is captured and used. This paper includes a significant improvement over the process compensated scheme in [12] as a completely digital system is used in the BIST controller in order reduce the design and layout complexity.…”

“…Prior proposals such as [12] have frequency independent, scalable BIST schemes -this paper offers a significant improvement in terms of silicon area and robustness as a fully digital self test scheme is used. While both schemes offer process independence, lower area overhead and absence of any analog components makes this proposal efficient to implement as compared to [12].…”

“…While both schemes offer process independence, lower area overhead and absence of any analog components makes this proposal efficient to implement as compared to [12].…”

“…Due to the closed-loop nature of the individual blocks, the observed integrated PD output can be represented as a sum of convolutions of successive parameters -M [P D out ] = max m=min M odule i [m].M odule i+1 [n − m](12) for, M odule i : i th module in the closed loop.…”