Closed-Loop Nonlinear Modeling of Wideband$SigmaDelta$Fractional-$N$Frequency Synthesizers

Hedayati, Hiva; Bakkaloglu, Bertan; Khalil, Waleed

doi:10.1109/tmtt.2006.882872

Cited by 52 publications

(25 citation statements)

References 19 publications

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“…This will improve the linearity of the phase detector (PD), which is composed of PFD and CP. As a result, noise generated by the SDM and folded down to small frequency offsets in the nonlinear PD is reduced, as described in [31,32,33,34,35]. Second, the PD linearity will be further improved by reducing turnon and turn-off time of CP1 in the fine tuning loop.…”

Section: Measurement Resultsmentioning

confidence: 99%

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

Peters

Osmany

et al. 2010

Analog Integr Circ Sig Process

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We present an integrated fractional-N lownoise frequency synthesizer for satellite applications. By using two integrated VCOs and combining digital and analog tuning techniques, a PLL lock range from 8 to 12 GHz is achieved. Due to a small VCO fine tuning gain and optimized charge pump output biasing, the phase noise is low and almost constant over the tuning range. All 16 sub-bands show a tuning range above 900 MHz each, allowing temperature compensation without sub-band switching. This makes the synthesizer robust against variations of the device parameters with process, supply voltage, temperature and aging. The measured phase noise is -87 dBc/Hz and -106 dBc/Hz at 10 kHz and 1 MHz offset, respectively. In integer-N mode, phase noise values down to -98 dBc/Hz at 10 kHz and -111 dBc/Hz at 1 MHz offset, respectively, were measured.

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Section: Measurement Resultsmentioning

confidence: 99%

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

Peters

Osmany

et al. 2010

Analog Integr Circ Sig Process

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“…Modulation-dependant second-order effects such as Charge Pump mismatches (static and dynamic), Phase-Frequency Detector dead zones, and divider delay also affect the output phase noise [3]- [5]. However, the most dominant of these noise sources is the charge pump (CP) static mismatch (between the up and down current, usually given in percent mismatch ρ mismatch ) [4]. Hence, only this modulationdependant noise source will be considered here.…”

Section: B Phase Noise Contributionmentioning

confidence: 99%

Multimode Reconfigurable Digital $\Sigma\Delta$ Modulator Architecture for Fractional-$N$ PLLs

Sleiman

Ismail

2010

IEEE Trans. Circuits Syst. II

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This brief presents the analysis, design, and implementation of a multimode reconfigurable digital Sigma-Delta (ΣΔ) modulator for use in fractional-N phase-locked loops. Analysis of second-, third-, and fourth-order modulators with respect to PLL phase noise contribution in the presence of loop nonlinearities is performed. Optimal architectures in each order are found and a single reconfigurable modulator is designed and implemented on FPGA. The proposed architecture is able to cover seven different modes of operation and spans three orders, thus offering a great degree of noise-shaping flexibility suitable for multistandard wireless applications. A case study for LTE/WiMAX is further presented for demonstration.

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“…However, several sources of error result in a nonlinear PFD/CP transfer characteristic (the charge dumped into loop filter Q[n] versus the time difference between PFD inputs ΔT [n]), as shown in Fig. 3(a) [25], [26]. For small ΔT [n], the PFD may not respond at all, resulting in the socalled PFD dead zone.…”

Section: A Pfd/cp Nonlinearitymentioning

confidence: 99%

Fractional-$N$ Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial

Pamarti

2009

IEEE Trans. Circuits Syst. II

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Closed-Loop Nonlinear Modeling of Wideband$SigmaDelta$Fractional-$N$Frequency Synthesizers

Cited by 52 publications

References 19 publications

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

An integrated 8-12 GHz fractional-N frequency synthesizer in SiGe BiCMOS for satellite communications

Multimode Reconfigurable Digital $\Sigma\Delta$ Modulator Architecture for Fractional-$N$ PLLs

Fractional-$N$ Phase-Locked-Loop-Based Frequency Synthesis: A Tutorial

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