CMOS bi-directional ultra-wideband galvanically isolated die-to-die communication utilizing a double-isolated transformer

Javid, Mahdi; Ptacek, Karel; Burton, R.S.; Kitchen, Jennifer

doi:10.1109/ispsd.2018.8393609

Cited by 7 publications

(2 citation statements)

References 4 publications

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“…The use of two series-connected galvanic isolation barriers, namely double isolation, can be exploited to improve the overall isolation rating. This is a viable solution for digital isolators (i.e., only data transfer) [13], with a maximum V SURGE around 13 kV by using a couple of isolation capacitors [14].…”

Section: Technologies For Chip-scale Galvanic Isolatorsmentioning

confidence: 99%

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

et al. 2020

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This paper exploits an effective approach to overcome the breakdown limitations of traditional galvanic isolators based on chip-scale isolation barriers, thus achieving a very high isolation rating (i.e., compliant with the reinforced isolation requirements). Such an approach is based on radio frequency (RF) planar coupling between two side-by-side co-packaged chips. Standard packaging along with proper assembling techniques can be profitably used to go beyond 20-kV surge voltage without using expensive or exotic isolation components. As a proof of concept, a bidirectional data transfer system based on RF planar coupling able to withstand an isolation rating as high as 25 kV has been designed in a low-cost standard 0.35-µm CMOS technology. Experimental measurements demonstrated a maximum data rate of 40 Mbit/s using a carrier frequency of about 1 GHz. The adopted approach also guarantees a common mode transient immunity (CMTI) of 250 kV/µs, which is a first-rate performance in view of next generation galvanic isolators for wide-bandgap power semiconductor devices, such as gallium nitride high-electron mobility transistors (GaN HEMTs) and silicon carbide (SiC) MOSFETs.

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Section: Technologies For Chip-scale Galvanic Isolatorsmentioning

confidence: 99%

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

et al. 2020

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“…Two series-connected on-chip thick dioxide capacitors are used in [7] to achieve a 12.8-kV surge voltage and a CMTI of 100 kV/µs at a data rate of 100 Mb/s. A double-isolation channel consisting of two series-connected integrated transformers demonstrated an 11-kV pk isolation in [17], but no CMTI performance was reported. A 20-kV PK surge voltage and a CMTI of 200 kV/µs are claimed in [18] along with a current consumption of 2.8 mA at a data rate of 1 Mb/s.…”

Section: Introductionmentioning

confidence: 99%

A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers

Spina,

Raimondi,

Castorina

et al. 2024

IEEE Trans. VLSI Syst.

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This article presents the design of a three-channel package-scale galvanic isolation interface for SiC and GaN power switching converters. The isolation interface consists of two side-by-side co-packaged chips fabricated in a low-cost 0.32-µm bipolar CMOS-DMOS (BCD) technology and includes three isolation data channels based on RF-coupled integrated microantennas. The isolation interface provides a channel for the gate driver control, a bidirectional channel for diagnostic, and a channel for the isolated power supply control. They use on-off keying (OOK)-modulated RF carriers of 1.5, 0.5, and 1.5 GHz, respectively. The galvanic isolation interface provides a maximum signal rate of 2 and 1.9 MHz for the driver and the power control channels, respectively, whereas the diagnostic channel guarantees half-duplex bidirectional communication up to 15 MHz. Thanks to the package-scale isolation approach, both reinforced galvanic isolation and first-rate common-mode transient immunity (CMTI) are achieved. High immunity to adjacent channel crosstalk is guaranteed by using channel frequency/physical separation. To best of the authors' knowledge, this is the first implementation of a package-scale galvanic isolation interface with three independent communication channels, including a bidirectional channel, in silicon technology.

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Reinforced Galvanic Isolation: Integrated Approaches to Go Beyond 20-kV Surge Voltage (invited)

Ragonese

Spina

Parisi

et al. 2020

Lecture Notes in Electrical Engineering

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CMOS bi-directional ultra-wideband galvanically isolated die-to-die communication utilizing a double-isolated transformer

Cited by 7 publications

References 4 publications

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

A CMOS Data Transfer System Based on Planar RF Coupling for Reinforced Galvanic Isolation with 25-kV Surge Voltage and 250-kV/µs CMTI

A Three-Channel Package-Scale Galvanic Isolation Interface for Wide Bandgap Gate Drivers

Reinforced Galvanic Isolation: Integrated Approaches to Go Beyond 20-kV Surge Voltage (invited)

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