This paper exploits an effective approach to overcome the breakdown limitations of traditional galvanic isolators based on chip-scale isolation barriers, thus achieving a very high isolation rating (i.e., compliant with the reinforced isolation requirements). Such an approach is based on radio frequency (RF) planar coupling between two side-by-side co-packaged chips. Standard packaging along with proper assembling techniques can be profitably used to go beyond 20-kV surge voltage without using expensive or exotic isolation components. As a proof of concept, a bidirectional data transfer system based on RF planar coupling able to withstand an isolation rating as high as 25 kV has been designed in a low-cost standard 0.35-µm CMOS technology. Experimental measurements demonstrated a maximum data rate of 40 Mbit/s using a carrier frequency of about 1 GHz. The adopted approach also guarantees a common mode transient immunity (CMTI) of 250 kV/µs, which is a first-rate performance in view of next generation galvanic isolators for wide-bandgap power semiconductor devices, such as gallium nitride high-electron mobility transistors (GaN HEMTs) and silicon carbide (SiC) MOSFETs.

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This paper presents the design of on-chip micro-antennas for package-scale galvanic isolators based on RF planar coupling. A step-by-step design procedure is proposed, which aims at the maximization of the weak electromagnetic coupling between the RX and TX antennas integrated on side-by-side co-packaged chips to enable both high isolation rating and common-mode transient immunity thanks to the high dielectric strength and low capacitive parasitics of a molding compound-based galvanic barrier, respectively. Micro-antenna design guidelines are drawn, highlighting the main relationship between coil coupling performance and their layout parameters, which are often in contrast with respect to traditional integrated inductor ones.

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