This paper presents the design of on-chip micro-antennas for package-scale galvanic isolators based on RF planar coupling. A step-by-step design procedure is proposed, which aims at the maximization of the weak electromagnetic coupling between the RX and TX antennas integrated on side-by-side co-packaged chips to enable both high isolation rating and common-mode transient immunity thanks to the high dielectric strength and low capacitive parasitics of a molding compound-based galvanic barrier, respectively. Micro-antenna design guidelines are drawn, highlighting the main relationship between coil coupling performance and their layout parameters, which are often in contrast with respect to traditional integrated inductor ones.

This paper presents an extensive comparison of two 28-nm CMOS technologies, i.e., standard and mm-wave-optimized (i.e., thick metals and intermetal oxides) back-end-of-line (BEOL). The proposed comparison is carried out at both component and circuit level by means of a quantitative analysis of the actual performance improvements due to the adoption of a mm-wave-optimized BEOL. To this end, stand-alone transformer performance is first evaluated and then a complete mm-wave macroblock is investigated. A 77-GHz down-converter for frequency modulated continuous wave (FMCW) long-range/medium range (LR/MR) radar applications is exploited as a testbench. For the first time, it is demonstrated that thicker metals and intermetal oxides do not guarantee significant improvements at mm-wave frequencies and a standard (low-cost) BEOL is competitive in comparison with more complex (expensive) ones.

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In this paper, the effect of a metal patterned ground shield (PGS) on the performance of monolithic inductors is investigated. To this aim, three spiral inductors integrated in a 28‐nm fully depleted (FD) silicon‐on‐insulator (SOI) CMOS technology are analyzed by means of a 3‐D FEM‐based commercial software. The inductors have been designed at different operating frequencies in the RF and mm‐wave ranges to better explore the effect of the PGS. Extensive analysis revealed that the shield is able to improve the quality factor (Q‐factor) only of the inductor operated at the lowest frequency (ie, K‐band). On the contrary, it has a detrimental effect on the Q‐factor of the inductors working at higher frequencies. This is mainly due to induced losses in the PGS itself, which are so high to frustrate the substrate loss reduction. This result gives a different perspective to the adoption of the PGS for CMOS integrated inductors, which is largely recommended to improve inductor performance in the current state of the art.

This brief presents a novel class-D oscillator topology conceived for galvanically isolated data transfer based on RF planar coupling. In its general implementation, it consists of n capacitively coupled stacked class-D oscillators, each one loaded by a primary transformer winding. Capacitive coupling between the oscillators guarantees robust frequency/phase synchronization. The oscillation voltages are combined at the secondary transformer winding, thus ideally producing the same oscillation amplitude of a class-D topology with a power consumption reduced by a factor of 1/n thanks to the current-reuse configuration. With respect to traditional topologies, capacitive-coupled stacked class-D oscillators also allow standard MOS transistors (i.e., with a low breakdown voltage) to be reliably operated at higher supply voltages. The oscillator advantages have been highlighted in comparison with the traditionally adopted complementary cross-coupled topology within an isolated data link based on RF planar coupling in a 0.18-µm CMOS technology.