CMOS compatible manufacturing of a hybrid SET-FET circuit

Abstract

This study analyzes feasibility of CMOS-compatible manufacturing of a hybrid Single Electron Transistor – Field Effect Transistor (SET-FET) circuit. The fundamental element towards an operating SET at room temperature is a vertical nanopillar with embedded Si nanodot generated by ion-beam irradiation. The integration process from nanopillars to contacted SETs is validated by structural characterization. Then, the monolithic fabrication of planar FETs integrated with vertical SETs is presented, and its compatibility with standard CMOS technology is demonstrated. The work includes process optimization, pillar integrity validation, electrical characterization and simulations taking into account parasitic effects. The FET fabrication process is adapted to meet the requirements of the pre-fabricated nanopillars. Overall, this work establishes the groundwork for the realization of a hybrid SET-FET circuit operating at room temperature.

CMOS-compatible manufacturability of sub-15 nm Si/SiO2/Si nanopillars containing single Si nanodots for single electron transistor applications

“…In the Ions4SET project [68] further work was carried out to fabricate and electrically characterize NPs with Si NDs and single SETs [69]. Moreover, the entire integration schema for a hybrid SET/FET device was elaborated and tested [30]. An important issue was to verify that the NPs/NDs could withstand the thermal, mechanical and chemical stresses of a complex SET/FET fabrication flow.…”

“…The integration of the NP/ND structures into the complex technology of SET/FET circuit fabrication is published in a separate paper [30]. The technologies introduced in both publications offer a unique path for the manufacturability of RT operating SETs and integrated SET/FET circuits.…”