CMOS Distributed Amplifiers Using Gate–Drain Transformer Feedback Technique

Hsiao, Ching Hung; Su, Tzu-Yu; Hsu, Shawn S. H.

doi:10.1109/tmtt.2013.2271614

Cited by 41 publications

(18 citation statements)

References 21 publications

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“…In the RF power amplifier (PA) applications, transistors are usually biased in the saturation region [4,5] to prevent from avalanche effects influenced. Nevertheless, avalanche operation of transistors is found to be beneficial to improvement of power performance, and this concept is applied for PA designs [6,7].…”

Section: Resultsmentioning

confidence: 99%

Compact MM‐wave CMOS distributed amplifier using series‐peaking line and M‐derived section

Lee

Yoon

Rieh

et al. 2015

Micro & Optical Tech Letters

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An mm‐wave distributed amplifier (DA) with high gain‐bandwidth (GBW) product and small chip area is implemented in a 65‐nm CMOS process. The DA consists of five cascode unit cells for high gain and isolation. To achieve a wide bandwidth, a series‐peaking line and an m‐derived section are inserted at the interstage and output networks, respectively, of each cascode unit cell. The transistor size is optimized for compromising the tradeoff between gain and bandwidth. For compact layout, all matching sections and lines are implemented using the microstrip structure. The DA exhibits a measured gain of 8.2 dB and a 3‐dB bandwidth of 65 GHz, thus reaching a GBW of 163 GHz. The return loss at the input and output are both more than 13 dB over the entire bandwidth. Due to compact layout, the chip occupies only 0.5 mm2. © 2015 Wiley Periodicals, Inc. Microwave Opt Technol Lett 57:814–817, 2015

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Section: Resultsmentioning

confidence: 99%

Compact MM‐wave CMOS distributed amplifier using series‐peaking line and M‐derived section

Lee

Yoon

Rieh

et al. 2015

Micro & Optical Tech Letters

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“…Based on the principle of transmission line (TML), the intrinsic parasitic capacitances of the active devices combine with the external inductive components to form the artificial TMLs, and a wide bandwidth can be obtained [6]- [9]. Fig.…”

Section: A Distributed Amplifiermentioning

confidence: 99%

“…The supply voltage suggested by the foundry for the adopted 90-nm RF CMOS is 1.2 V (maximum up to ~ 1.5 V) to avoid transistor breakdown and ensure long-term reliability. The cascode configuration is often used to enhance the output voltage swing [6]- [7]. However, the gate bias of the CG stage is fixed in a typical cascode gain cell, and hence the transistor could encounter the breakdown situation if a large swing appears at the drain node of the cascode cell.…”

Section: B Modified Cascode Stagementioning

confidence: 99%

A 40-Gb/s 4-V_pp Differential Modulator Driver in 90-nm CMOS

Chiu

et al. 2018

IEEE Microw. Wireless Compon. Lett.

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“…The shunt-peaking amplifiers [11]- [12] can also provide flat gain over a wide frequency band, but they cannot provide high output power due to a voltage drop across a resistive load. The distributed amplifiers [13]- [14] tend to consume a large amount of dc current due to the distribution of multiple amplifying stages. In Fig.…”

Section: Drive Amplifier I-q Phase Modulatormentioning

confidence: 99%

3-Level Envelope Delta-Sigma Modulation RF Signal Generator for High-Efficiency Transmitters

Seo¹,

Cho

Choi

et al. 2014

ETRI J

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This paper presents a 0.13 μm CMOS 3-level envelope delta-sigma modulation (EDSM) RF signal generator, which synthesizes a 2.6 GHz-centered fully symmetrical 3-level EDSM signal for high-efficiency power amplifier architectures. It consists of an I-Q phase modulator, a Class B wideband buffer, an up-conversion mixer, a D2S, and a Class AB wideband drive amplifier. To preserve fast phase transition in the 3-state envelope level, the wideband buffer has an RLC load and the driver amplifier uses a second-order BPF as its load to provide enough bandwidth. To achieve an accurate 3-state envelope level in the up-mixer output, the LO bias level is optimized. The I-Q phase modulator adopts a modified quadrature passive mixer topology and mitigates the I-Q crosstalk problem using a 50% duty cycle in LO clocks. The fabricated chip provides an average output power of 1.5 dBm and an error vector magnitude (EVM) of 3.89% for 3GPP LTE 64 QAM input signals with a channel bandwidth of 10/20 MHz, as well as consuming 60 mW for both channels from a 1.2 V/2.5 V supply voltage.Keywords: CMOS, envelope delta-sigma modulation, EDSM, power amplifier, polar modulator, RF transmitter, 3GPP LTE. Manuscript received Feb. 18, 2014; revised July 3, 2014; accepted Aug. 5, 2014. This work was supported by National Research Foundation of Korea Grant funded by the Korean Government and also supported by the ICT R&D Program of MSIP/IITP (14-000-04-001, Development of 5G Mobile Communication Technologies for Hyper-connected Smart Services).Yongho Seo (syh3039@hanmail.net) I. IntroductionIn high-data-rate wireless systems, such as 3GPP Long-Term Evolution (LTE) and Worldwide Interoperability for Microwave Access (WiMAX), tremendous efforts to enhance power amplifier (PA) efficiency have led to new transmitter architectures employing a particular 1-bit encoder, such as delta-sigma modulation (DSM) or pulse-width modulation (PWM) [1]- [4]. However, due to such encoders having low coding efficiency, excessive power loss and efficiency degradation cannot be avoided. To enhance the cording efficiency of an encoder, we previously proposed the new transmitter architecture [5] shown in Fig. 1. In Fig. 1, a multilevel envelope delta-sigma modulation (ML-EDSM) scheme is used to enhance the coding efficiency using a 3-level (zero, A(t) max /2, and A(t) max ) envelope signal instead of a conventional 2-level signal. However, 3-level envelope modulation can degrade the PA efficiency, as the PA cannot operate in a saturated region under a single supply voltage for a middle-level envelope signal A(t) max /2. To overcome this problem, a dual-supply injection method is applied in the PA, as shown in Fig. 1. For the maximum-level envelope signal, A(t) max , the PA operates in the saturated region under a high supply voltage of V DD1 . However, when A(t) max becomes A(t) max /2, the dual-supply network switches V DD1 (V DD1 > V DD2 ) to the low supply voltage of V DD2 concurrently. Accordingly, the PA can always operate in the saturated region for the 3-level ...

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CMOS Distributed Amplifiers Using Gate–Drain Transformer Feedback Technique

Cited by 41 publications

References 21 publications

Compact MM‐wave CMOS distributed amplifier using series‐peaking line and M‐derived section

Compact MM‐wave CMOS distributed amplifier using series‐peaking line and M‐derived section

A 40-Gb/s 4-V_pp Differential Modulator Driver in 90-nm CMOS

3-Level Envelope Delta-Sigma Modulation RF Signal Generator for High-Efficiency Transmitters

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CMOS Distributed Amplifiers Using Gate–Drain Transformer Feedback Technique

Cited by 41 publications

References 21 publications

Compact MM‐wave CMOS distributed amplifier using series‐peaking line and M‐derived section

Compact MM‐wave CMOS distributed amplifier using series‐peaking line and M‐derived section

A 40-Gb/s 4-Vpp Differential Modulator Driver in 90-nm CMOS

3-Level Envelope Delta-Sigma Modulation RF Signal Generator for High-Efficiency Transmitters

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Product

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A 40-Gb/s 4-V_pp Differential Modulator Driver in 90-nm CMOS