CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

Paul, Anindita; Ramírez-Angulo, J.; Lopez-Martin, A.J.; Carvajal, R.G.

doi:10.1109/tvlsi.2018.2878017

Cited by 8 publications

(13 citation statements)

References 25 publications

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“…It also omits low-frequency signals from the processing in these devices when AC coupling between internal stages or cells (functional blocks respectively) is required. However, applications operating with very low frequencies receive increasing attention (see for example integrated filters for the field of Hz and sub-Hz bands [2], [3]) because low-frequency responses are typical in sensing of nonelectrical quantities (for instance lowfrequency vibrations and seismic activities [4]- [6]). It is necessary to use AC coupling in complex processing systems because of many reasons (e.g.…”

Section: A Motivation Of the Designmentioning

confidence: 99%

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Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

et al. 2021

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This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the of values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

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Section: A Motivation Of the Designmentioning

confidence: 99%

“…The analog multiplier represents the key part of our design. The basic principle of the multiplier can be studied in [10] and [11]. Many other solutions have been presented in recent literature.…”

Section: Cmos Multipliermentioning

confidence: 99%

Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

et al. 2021

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“…One solution to this issue is to employ compact all‐pass filter structures as TTD cells in these frequencies [15]. However, in many cases, passive inductors are used to ensure the wideband performance of the structure [9].…”

Section: Introductionmentioning

confidence: 99%

“…Unfortunately, the inductor-based TTD cells are in contrast with these characteristics. Hopefully, some designs presented inductor-less TTD cells for addressing this matter [9,16].…”

Section: Introductionmentioning

confidence: 99%

A PVT resilient true‐time delay cell

Yarahmadi

Jannesari

2023

IET Circuits, Devices & Syst

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A true-time delay (TTD) cell in TSMC 0.18 μm CMOS technology for 1-5 GHz applications is presented. Process variations, ageing effects, field variations, and other non-idealities have some impacts on the TTD cell's devices. One of the vulnerable specifications of TTD cells is their delay variation. While the TTD cell works in a delay line, the cell must have a constant and robust delay in the frequency band. For this matter, the body bias technique is presented and applied to the inductor-less TTD cell. With this technique, the threshold voltage can be manipulated intentionally. So, any variation in this voltage can be compensated with the body biasing of transistors. The simulation results show the TTD cell's robust performance against non-idealities, while delay variation improves more than 3� times in the frequency band of interest. This TTD cell provides a 50.95 pS delay with only 2% variation, while S 11 and S 22 parameters are lower than −10 dB in the 1-5 GHz frequency band. IIP3 of the TTD cell is about 2.7 dBm, and the power consumption is 20.5 mW. K E Y W O R D Sall-pass filter, active filters, analogue integrated circuits, CMOS analogue integrated circuits, continuous time systems, integrated circuit design, low-power electronics, radio frequency filters, Timed array system, True-Time-Delay cellThis is an open access article under the terms of the Creative Commons Attribution-NonCommercial-NoDerivs License, which permits use and distribution in any medium, provided the original work is properly cited, the use is non-commercial and no modifications or adaptations are made.

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“…At the same time, large dynamic currents can be provided, since signals are capacitively coupled to the high impedance gate node. Due to these advantages, QFG transistors have found widespread use in the design of amplifiers but also in high-performance current mirrors [31][32][33][34][35], mixers [36,37], linearization of active resistors [38,39], DC offset cancellation servo loop circuits [40], bootstrapped switches [5], current conveyors [30,[41][42][43], Voltage Feedback Operational Amplifiers (VFOAs) [44], Current Feedback Operational Amplifiers (CFOAs) [45], buffers [46][47][48][49][50][51], rectifiers [35,52], capacitance multipliers [35], transconductors [30,[53][54][55], digital-based analog circuits [56], DC-DC converters [57], continuous-time filters [58][59][60][61], track and hold circuits [5], data converters [5,62], capacitive sensing interfaces [63], particle detectors [23] and retinal prosthesis [64], to name some representative applications.…”

Section: Introductionmentioning

confidence: 99%

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

et al. 2021

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Energy efficiency is a key requirement in the design of amplifiers for modern wireless applications. The use of quasi-floating gate (QFG) transistors is a very convenient approach to achieve such energy efficiency. We illustrate different QFG circuit design techniques aimed to implement low-voltage, energy-efficient class AB amplifiers. A new super class AB QFG amplifier is presented as a design example, including some of the techniques described. The amplifier has been fabricated in a 130 nm CMOS test chip prototype. Measurement results confirm that low-voltage, ultra-low-power amplifiers can be designed, preserving, at the same time, excellent small-signal and large-signal performance.

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CMOS First-Order All-Pass Filter With 2-Hz Pole Frequency

Cited by 8 publications

References 25 publications

Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

A PVT resilient true‐time delay cell

Energy-Efficient Amplifiers Based on Quasi-Floating Gate Techniques

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