2013
DOI: 10.1007/978-1-4614-4280-6
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CMOS Integrated Capacitive DC-DC Converters

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Cited by 50 publications
(39 citation statements)
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“…First, the tuning range of the input impedance has to be expanded; as a result of an improved energy harvest source, its source impedance is decreased to 1 Ω. Second, silicon area is limited to handle more power with an switched capacitor converter; half of energy is lost when charges are transferred through capacitors [11]. However, on-chip capacitance given by a technology is a few fF per micrometer square.…”
Section: The Open Problemsmentioning
confidence: 99%
“…First, the tuning range of the input impedance has to be expanded; as a result of an improved energy harvest source, its source impedance is decreased to 1 Ω. Second, silicon area is limited to handle more power with an switched capacitor converter; half of energy is lost when charges are transferred through capacitors [11]. However, on-chip capacitance given by a technology is a few fF per micrometer square.…”
Section: The Open Problemsmentioning
confidence: 99%
“…The stimulation voltage is derived from the main supply by using an 1 : 1 switched-capacitor DC-DC converter. This particular topology of DC-DC converter operates as a resistor [2]. The further away the output voltage is from the input voltage, the lower the power efficiency is.…”
Section: Comments and Correctionsmentioning
confidence: 99%
“…This widely used model [5], reveals that R out has to be controllable in order to maintain a desired V out when both V in and I load are varying given that N = 1/3 is fixed by the topology. The expressions for R out in the two extremes, slow switching limit (SSL) and fast switching limit (FSL), for when the switching period is much greater or smaller than the time constant of C f ly and the switch resistance, shows how R out depends on R sw and F sw [3]:…”
Section: A Output Stage Fundamentalsmentioning
confidence: 99%