CMOS Latch-Up Characterization using a Laser Scanner

Henley, Francois J.; Chi, Min-Hwa; Oldham, W.G.

doi:10.1109/irps.1983.361972

Cited by 13 publications

(5 citation statements)

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“…The desired effect is the perturbation of the IC electric properties by carrier generation in the silicon, photoelectric effect [1,2,3]. A wide range of defect or anomalies can be localized with these techniques based on Photoelectric Laser Stimulation: like junctions issues, open or latch up sensitivity [4] and recently dynamic applications have been developed, we can mention LADA [5].…”

Section: Laser Stimulation Principlementioning

confidence: 99%

Dynamic Thermal Laser Stimulation Theory and Applications

Sanchez

Desplats

Beaudoin

et al. 2006

2006 IEEE International Reliability Physics Symposium Proceedings

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Thermal Laser Stimulation (TLS) techniques have demonstrated their ability to detect and locate defects in integrated circuits (IC). Optical Beam Induced Resistance Change (OBIRCH) and all derivatives are based on the same physical principle: local laser heating of integrated circuits.The purpose of this paper is to synthesize the extensive work done in this area in order to highlight the essential physical principles. With this knowledge Dynamic Thermal Laser Stimulation (D-TLS) applications can then be tackled, optimizing parameters such as laser dwell time for sufficient heating. Finally, applications will be presented on 180nm, 120nm and 90nm, comparing the sensitivity of Dynamic Thermal Laser Stimulation with respect to light emission.

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Section: Laser Stimulation Principlementioning

confidence: 99%

Dynamic Thermal Laser Stimulation Theory and Applications

Sanchez

Desplats

Beaudoin

et al. 2006

2006 IEEE International Reliability Physics Symposium Proceedings

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“…Techniques for the study of local latch-up sensitivity adopt a focused laser [33] or electron beam [30] as a localized current generator, as indicated in Fig. 12 a).…”

Section: Scanning Laser Microscopy F O R the Sludy Of Thementioning

confidence: 99%

VLSI reliability: Contributions from a three year national research program

Soncini

Canali

Zanoni

et al. 1990

Trans Emerging Tel Tech

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The continuous trend to further I.C. miniaturization implies increased local electric field strength and power dissipation density, and a perverse scaling, behaviour of metal interconnections and contacts. This will result in new failure mechanisms while old ones, non under control, may become a threat again. This work reports on the most relevant results, related to VLSI reliability, obtained by the seven University Research Teams involved in a three years Research Program sponsored by the Italian Ministero Pubblica Istruzione. In particular new methods to investigate electromigration and to localize latch‐up phenomena have been successfully developed. Also test and diagnosis techniques to analyze faults in digital I.C. with emphasis on ECL and custom VLSI have been studied, and electromagnetic interference effects, in operational amplifiers have been modelled and simulated.

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“…The evaluation of latch-up sensitivity on CMOS ICs has been performed by means of laser scanner analyzers ( Henley et al 1983, Shiragasawa et al 1984. The device is kept normally biased; parasitic SCR structures are initially in the off state.…”

Section: Techniques For the Measurement Of Local Latch-up Sensitivitymentioning

confidence: 99%

“…(a) it is necessary to establish a correlation between electrical behaviour and photoelectric measurements, and this correlation must be updated with changing technology; (b) the large currents resulting from carrier generation can alter the normal behaviour of the device; (c) the relatively high laser power densities required may induce unwanted thermal effects; (d) the amount of carrier generated in the semiconductor markedly depends on the absorption of the upper layers; (e) the time required to form a 50 x 50 image is reported to be of the order of 12 min ( Henley et al 1983).…”

Section: Techniques For the Measurement Of Local Latch-up Sensitivitymentioning

confidence: 99%

An SEM based system for a complete characterization of latch‐up in CMOS integrated circuits

Canali

Fantini²,

Giannini³

et al. 1986

Scanning

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An electron beam testing system was established for a complete and detailed analysis of latch‐up in CMOS integrated circuits. Problems which can be studied include: identification of latch‐up current paths in steady state condition; measurement of the local latch‐up sensitivity of the various parts of the circuit; observation of the time evolution of latch‐up from the firing event to the final condition.

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CMOS Latch-Up Characterization using a Laser Scanner

Cited by 13 publications

References 0 publications

Dynamic Thermal Laser Stimulation Theory and Applications

Dynamic Thermal Laser Stimulation Theory and Applications

VLSI reliability: Contributions from a three year national research program

An SEM based system for a complete characterization of latch‐up in CMOS integrated circuits

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