CMOS Low Noise Amplifier Topology Using Compact Wu Folded Active Inductor

Cambero, Eduardo Vicente Valdés; Muñoz, Rodrigo Reina; Casella, Ivan R. S.; Filho, Alfeu J. Sguarezi; Araujo, H. X.; Capovilla, C. E.

doi:10.1109/tla.2017.8071223

Cited by 5 publications

(1 citation statement)

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“…Various types of AI are used to design the circuits such as Wu folded compact (WFC) and CFR AI. Figure 22, [20], shown below is the circuit of LNA-PDAI (Low noise amplifier-Partially degenerated Active Inductor) in which all the inductors are replaced by on-chip inductors, and the one-stage cascode LNA with PDAI has better gain and better linearity with a moderate bandwidth at the cost of power consumption because of increase if intermediate stages.…”

Section: Recent Advancements In Lna Architecturementioning

confidence: 99%

On-Chip Tunable Active Inductor Circuit for Radio Frequency Ics

Prashar,

Kapur

2023

Wseas Transactions on Electronics

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The work presents a design of a gyrator-based on-chip tunable active inductor (AI) which can become an integral part of high-frequency integrated circuits. The proposed AI uses the Floating gate technology-based PMOS (FGPMOS) simulation model, where the on-chip, non-volatile programming ability of FGPMOS is used as a tunable active feedback resistor. The circuit specifications are first derived for the application at 800MHz to 2GHz. The design is simulated at 350nm CMOS technology and shows a temperature sensitivity of 0.13mV/oC as well as a noise sensitivity of about 10.97nV/Hz. The precise programming range of inductance value from 3nH to 9nH can be achieved. The circuit has a power dissipation of 5.02mV and a moderately high-quality factor of about 120. The layout of the proposed circuit has been designed on Cadence Virtuoso and fabricated at ON-Semiconductor, C5 CMOS process foundry of MOSIS fabrication service, USA. The complete design has a chip area of 18x30µm2. The fabricated results illustrate the on-chip tuning ability of the proposed AI from 3nH to 7nH with the help of externally applied Tunnelling and Injection voltages, respectively. The proposed design also simulates a tunable bandpass filter and a tunable Low Noise Amplifier.

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Section: Recent Advancements In Lna Architecturementioning

confidence: 99%