CMOS RF Low-Noise Amplifier Design for Variability and Reliability

Liu, Yidong; Yuan, J.S.

doi:10.1109/tdmr.2011.2160350

Cited by 22 publications

(14 citation statements)

References 19 publications

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“…For the RIC, maximum improvement in variability is obtained for peak gain (up to 16.7%) against a varying supply and reduction in gain deviation against VPC and VTV is up to 8.3 and 12.3%, respectively. Therefore the RIC will increase the constancy of a front-end's gain profiles and is more effective in stabilising gain than [22,25] are able to improve gain fluctuation by < 2.5 and < 4.1% against alteration of device threshold and supply voltage. The references are selected to focus on similar circuit architectures (CMOS amplifiers) with [19] stabilitating a class AB power amplifier and [22] improving a cascode amplifier.…”

Section: Results Of Cmos Reliabilitymentioning

confidence: 99%

“…Therefore the RIC will increase the constancy of a front-end's gain profiles and is more effective in stabilising gain than [22,25] are able to improve gain fluctuation by < 2.5 and < 4.1% against alteration of device threshold and supply voltage. The references are selected to focus on similar circuit architectures (CMOS amplifiers) with [19] stabilitating a class AB power amplifier and [22] improving a cascode amplifier. Compensation circuits for LNAs are proposed in [23][24][25] with the help of features like switchable capacitance, reconfigurability and feedback schemes.…”

Section: Results Of Cmos Reliabilitymentioning

confidence: 99%

“…The objective of including a reliability improving circuit (RIC) in a CMOS architecture is to reduce variation in the system's figures of merit (FOM). Recent literature has addressed this issue for various radio frequency (RF), digital and digital-to-analog-conversion (DAC) circuits [5,[16][17][18][19][20][21][22][23][24][25][26][27][28][29]. For example, a reliability-sensitive power amplifier is presented in [5] which can be integrated with a wireless fidelity receiver to mitigate discharge/aging issues.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Common‐rail powered reliability improving technique for single‐supply complementary metal oxide semiconductor amplifiers

Roy¹,

Rashid²

2015

IET Circuits, Devices & Systems

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This paper presents a low-power technique to improve reliability of complementary metal oxide semiconductor (CMOS) amplifiers using a shared bias network for input gate and substrate of transistors. The circuit [named reliability improving circuit (RIC)] significantly reduces discrepancy in amplifier gain (S 21 , voltage gain), noise figure (NF/NF min) and output reflection-loss (ORL) parameters resulting from variation in threshold voltage, feature-width, device speed and supply rail. It performs well on both typical-(1.2 V) and low-voltage (0.7 V) platforms of a 90 nm CMOS technology and is able to maintain its consistency within a wide frequency coverage (10-30 GHz) for three different architectures (cascode, low-voltage cascode and common-source). This allows the RIC incorporated front-end to satisfy a broad range of gain, isolation, linearity and NF requirements. The scheme's biasing arrangement is powered from amplifier rails which permit the overall circuit to be driven from a single main supply. Analysis and simulation results demonstrate the technique improving consistency of figures of merit considerably against different aspects of process/system variation without significant degradation of radio frequency performance.

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Section: Results Of Cmos Reliabilitymentioning

confidence: 99%

Section: Results Of Cmos Reliabilitymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Common‐rail powered reliability improving technique for single‐supply complementary metal oxide semiconductor amplifiers

Roy¹,

Rashid²

2015

IET Circuits, Devices & Systems

View full text Add to dashboard Cite

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“…they are no longer matched to 50 purely real. It can be observed from Table V that the variation in real and imaginary part of the input impedance falls into one of the cases [6] which is shown in the Table VI. The substrate bias can be used to compensate the process variations [7]. To be specific the input impedance is a function of substrate voltage.…”

Section: Simulation Methodologymentioning

confidence: 99%

Mitigation of process variation in MOSFET-based narrowband LNA

Suresh¹,

Kumar²,

Nagarajan³

et al. 2014

International Conference on Information Communication and Embedded Systems (ICICES2014)

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In this paper, 45 nm gate length MOSFET-based LNA, operating at 5 GHz, is studied for the impact of process variation on LNA performance metrics such as input impedance, gain and noise figure. Gate length, channel width, gate oxide thickness, channel doping concentration, and source/drain doping concentration are considered as varying parameters. The effect of these variations on the input impedance (50 purely real) of LNA is compensated by substrate/body bias of bulk MOSFET. Most of the cases are mitigated using this technique.

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“…On the other hand, adaptability has been also used to mitigate the effects of process variations on CMOS-LNAs [3,[11][12][13][14][15]. The proposal presented by González et al [3] shows the potentials of an adaptable LNA to save power when its behavior under process variations remains close to the typical-case performance.…”

Section: Introductionmentioning

confidence: 99%

Energy-Aware Low-Power CMOS LNA with Process-Variations Management

González

Moreno

Cruz

et al. 2016

Active and Passive Electronic Components

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A reconfigurable low-noise amplifier (LNA) with digitally controllable gain and power consumption is presented. This architecture allows increasing power consumption only when required, that is, to improve LNA’s radiofrequency performance at extreme communication-channel conditions and/or to counteract the effect of process, voltage, and temperature variations. The proposed design leads to significant power saving when a relaxed operation is acceptable. The LNA is implemented in a 130 nm 1.2 V CMOS technology for a 2.4 GHz IEEE-802.15.4 application. Simulated LNA performance (taking into account the worst cases under process variations) is comparable to recently published works.

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CMOS RF Low-Noise Amplifier Design for Variability and Reliability

Cited by 22 publications

References 19 publications

Common‐rail powered reliability improving technique for single‐supply complementary metal oxide semiconductor amplifiers

Common‐rail powered reliability improving technique for single‐supply complementary metal oxide semiconductor amplifiers

Mitigation of process variation in MOSFET-based narrowband LNA

Energy-Aware Low-Power CMOS LNA with Process-Variations Management

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