CMOS technology for mixed signal ICs

Analog device design for low power mixed mode applications in deep submicron CMOS technology

“…This has enabled a new era in communications and multimedia applications, which requires further downsizing and low-power dissipation. However, deeply scaled CMOS device design for SOC applications is particularly challenging, since device performance requirements, like short channel effects (SCE), transconductance, and device gain; and analog circuit needs, like signal swing, signal-to-noise ratio (SNR), and power dissipation, often result in trade-offs and it has become essential to look for alternative structures to meet the analog requirements for mixed mode ICs [1]- [4].…”

A compact model of MOSFET mismatch for circuit design

“…As can be seen from the results, for NMOS and PMOS devices with the same geometry, inversion level, and drain voltage, PMOS (in compensated N-well) present higher mismatch than NMOS transistors. Other authors have found that PMOS show greater mismatch than NMOS devices [35], [36], while some have found the contrary [12]. We conclude that there is not a simple "rule of thumb" regarding which type of MOS transistor is better matched.…”

A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

“…Monte-Carlo simulations show 7m V dynamic offset due to transistor mismatch in threshold voltage [19], [20]. The offset can be much higher than the simulated taking into account of unbalanced clock feedthrough due to mismatch in the switch FET size and the node capacitance receiving the fed through charge.…”

“…(1), 85 dB SFDR requires about 11-12b quantizer. Given the CMOS comparator (with preamp) offset on the order of a few m V [ 19], [20] and available input full scale on the order of 2V, 12b resolution can not be realized without some technique either to effectively reduce the offset or effectively amplify the input full scale. Residue amplification [21], which effectively amplify the FS without running into headroom problem, is a common choice for CMOS ADC to overcome the excessive offsets.…”