A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

Pan, Hui; Segami, M.; Choi, Michael; Cao, Jing; Hatori, F.; Abidi, A.A.

doi:10.1007/978-1-4757-3198-9_3

Cited by 15 publications

(20 citation statements)

References 57 publications

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“…The second circuit [144] removes the bulk effect, but not the effect of the junction capacitances. There, the signal voltage is not directly connected to the gate of the switch device, but is first predistorted to account for the bulk effect.…”

Section: Eliminating the Bulk Effectmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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The increasing digitalization in all spheres of electronics applications, from telecommunications systems to consumer electronics appliances, requires analog-to-digital converters (ADCs) with a higher sampling rate, higher resolution, and lower power consumption. The evolution of integrated circuit technologies partially helps in meeting these requirements by providing faster devices and allowing for the realization of more complex functions in a given silicon area, but simultaneously it brings new challenges, the most important of which is the decreasing supply voltage.Based on the switched capacitor (SC) technique, the pipelined architecture has most successfully exploited the features of CMOS technology in realizing high-speed high-resolution ADCs. An analysis of the effects of the supply voltage and technology scaling on SC circuits is carried out, and it shows that benefits can be expected at least for the next few technology generations. The operational amplifier is a central building block in SC circuits, and thus a comparison of the topologies and their low voltage capabilities is presented.It is well-known that the SC technique in its standard form is not suitable for very low supply voltages, mainly because of insufficient switch control voltage. Two low-voltage modifications are investigated: switch bootstrapping and the switched opamp (SO) technique. Improved circuit structures are proposed for both. Two ADC prototypes using the SO technique are presented, while bootstrapped switches are utilized in three other prototypes.An integral part of an ADC is the front-end sample-and-hold (S/H) circuit. At high signal frequencies its linearity is predominantly determined by the switches utilized. A review of S/H architectures is presented, and switch linearization by means of bootstrapping is studied and applied to two of the prototypes. Another important parameter is sampling clock jitter, which is analyzed and then minimized with carefully-designed clock generation and buffering.The throughput of ADCs can be increased by using parallelism. This is demonii strated on the circuit level with the double-sampling technique, which is applied to S/H circuits and a pipelined ADC. An analysis of nonidealities in double-sampling is presented. At the system level parallelism is utilized in a time-interleaved ADC. The mismatch of parallel signal paths produces errors, for the elimination of which a timing skew insensitive sampling circuit and a digital offset calibration are developed. A total of seven prototypes are presented: two double-sampled S/H circuits, a time-interleaved ADC, an IF-sampling self-calibrated pipelined ADC, a current steering DAC with a deglitcher, and two pipelined ADCs employing the SO technique.

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Section: Eliminating the Bulk Effectmentioning

confidence: 99%

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Waltari¹,

Halonen²

2003

The International Series in Engineering and Computer Science

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“…Early pipeline ADC designs [1]- [8] focused on using circuit techniques to reduce the overall error level. On the other hand, self-calibration techniques [9]- [12] are able to compensate for a part of the systematic error, so as to provide ADC designs with higher resolution at lower power consumption or at higher speed.…”

Section: Introductionmentioning

confidence: 99%

Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter

Yuan

Farhat

Spiegel

2008

IEEE Trans. Circuits Syst. I

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A new all-digital background calibration method, using a piecewise linear model to estimate the stage error pattern, is presented. The method corrects both linear and nonlinear errors. The proposed procedure converges in a few milliseconds and requires low hardware overhead, without the need of a high-capacity ROM or RAM. The calibration procedure is tested on a 0.6-µm CMOS pipeline analog-to-digital converter (ADC), which suffers from a high degree of nonlinear errors. The calibration gives improvements of 17 and 26 dB for signal-noise-and-distortion ratio (SNDR) and spurious-free dynamic range (SFDR), respectively, for the Nyquist input signal at the sampling rate of 33 MSample/s. The calibrated ADC achieves SNDR of 70.3 dB and SFDR of 81.3 dB at 33 MSample/s, which results in a resolution of about 12 b. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it.This journal article is available at ScholarlyCommons: http://repository.upenn.edu/ese_papers/344 Index Terms-Analog-to-digital converter (ADC), background calibration, CMOS ADC, nonlinear error calibration, pipeline ADC.

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“…Let us sum up the error contributions from point 1-3 for the stage k and assume that e k = f k . Then the error contribution from the stage resembles the quantization error that the ADC would give if it was truncated right after stage k [84]. The difference is a factor of e k .…”

Section: Discussionmentioning

confidence: 99%

“…However, there exist clever solutions to reduce the number of comparators and references, like interpolation and folding [15,16,17].…”

Section: Flash Adcmentioning

confidence: 99%

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Floating-point analog-to-digital converter

Yuan

Piper²

ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357)

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To deal with the wide dynamic rage necessary for a radio receiver or corresponding applications, but to avoid impractically high resolution at high data rates, the approach of using a floating-point analog-to-digital converter (FP-ADC) has been investigated. This approach de-links the dynamic range with the resolution, and a very wide dynamic range can be achieved by an ADC with a moderate resolution.The solution for an FP-ADC presented in this thesis is to amplify the input signal in several channels using binary weighted gains. The channel output with the largest amplitude, but still within the ADC input range, will be selected for conversion. The binary weighting is obtained by dividing the input signal with passive divider and amplifying the divider outputs by identical amplifiers. The outputs from the amplifiers are sampled individually. The selected sampled signal is then converted by a pipelined ADC. The result from the selection gives the exponent and the ADC output the mantissa of the floating-point number.Issues on the specific problems of designing the proposed FP-ADC have been addressed, including a general discussion about a pipelined ADC along with its sub-blocks.A thorough investigation of the distortion in a pipelined ADC due to static mismatches and systematic errors is also presented. The result of the investigation is a general approach on how to calculate the distortion in a pipelined ADC. The distortion analyses can be performed by both analytical methods and computer simulations.A chip has been manufactured in a standard analog 0.35 µm CMOS process giving 10 bits of resolution, and a dynamic range corresponding to a 15-bit ADC. The sampling rate is 54 Ms/s using 330 mW of power. This project started when Pietro Andreani talked me into pursuing PhD studies within the Electroscience department, and to investigate an interesting problem Jiren Yuan, my supervisor, presented. While being with the department my knowledge has been deepened and broadened within the area of mixed signal design, and especially data converters.I have also had lots of fruitful discussions with my colleagues at the department. By keeping up a friendly atmosphere and a high academic ceiling, it has been fun and well worth spending so many years at the same place. Especially I would like to mention Roland Strandberg, Martin Lantz, Martin Andersson and Gang Xu who have been there to discuss everything from transistors physics to amplifier design to intricate problems in data converters. I would like to thank them for their enthusiasm and help.I would also thank Anders "J" Johansson and Lars Olsson for taking their time to check my spelling and grammar and helping me make this thesis more readable.No thesis would have been possible without the work of Erik Jonsson or Stefan Molund, who are constantly keeping the computers, network and tools up running day and night.In addition to this, I would also like to thank all other parties who have been involved in this process. I cannot mention you all by name, but I will al...

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A 3.3-V 12b 50-MS/s A/D Converter in 0.6-µm CMOS with over 80-dB SFDR

Cited by 15 publications

References 57 publications

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Circuit Techniques for Low-Voltage and High-Speed A/D Converters

Background Calibration With Piecewise Linearized Error Model for CMOS Pipeline A/D Converter

Floating-point analog-to-digital converter

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