CMOS technology for mixed signal ICs

Analog-to-Digital Conversion

“…Process options can be subdivided into four categories [246]: One level below the baseline technology there is more freedom: most foundries offer two or more generations of a process: a mature process with large feature sizes and a advanced shrink version.…”

“…Figure 11.18 shows an example of the measured dependence for σ V T versus 1/ √ area. The quantity N x z d was derived from process simulation which was tuned with accurate C/V measurements [246]. In this plot the lay-out dimensions were used.…”

Spatial filtering in flash A/D converters

“…Averaging exploits the higher SNR in the sum of many samples of a signal corrupted by uncorrelated noise (the random offsets). As an analogy, consider the random charges trapped in the gate oxide of a MOSFET and the random variation in the depletion charge density which cause the MOSFET threshold voltage to fluctuate randomly [12], [13]. These fluctuations may be averaged out by connecting many identical MOSFETs in parallel, equivalent to scaling up the MOSFET size.…”

“…1(a)] may not be zero if an offset current is injected to any node of the spatial filter. Offset currents arise from mismatch [12], [13] in the differential pairs and fluctuations in the tail currents of the ZX generators. Since offsets are usually within the linear region of the transistors, we have , where and are the transconductance and input referred voltage offset of the th diffpair, and is the error current injected to node due to random spreads in tail currents across the array.…”

A 14-bit MOSFET-only second order delta-sigma modulator for capacitive sensor interfaces

“…In CMOS digital technologies, without a second poly layer, it is difficult to have large capacitors due to the area that they need [4]. By using a digital 0.7pm CMOS technology (n-well, 1 poly layer, 2 metal layers), there are two possible ways to implement capacitors: (i) Sandwich capacitors with a total capacitance per area unit of 9.9.10' 5pF/pm2.…”