Spatial filtering in flash A/D converters

Pan, Hui; Abidi, A.A.

doi:10.1109/tcsii.2003.813584

Cited by 49 publications

(1 citation statement)

References 18 publications

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“…From Ref. [13], the error correction factor (ECF) is defined to give an optimum solution to design the spatial filter, ECF Á…”

Section: Interpolation Network and Resistive Averaging Techniquementioning

confidence: 99%

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-WB receiver

Zhao¹,

Wang²,

Qin³

et al. 2011

J. Semicond.

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A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier (THA) in 0.13 m CMOS for an impulse radio ultra-wideband (IR-UWB) receiver is presented. The challenge is in implementing a sub-sampling ADC with ultra-high input signal that further exceeds the Nyquist frequency. This paper presents, to our knowledge for the second time, a sub-sampling ADC with input signals above 4 GHz operating at a sampling rate of 1.056 GHz. In this design, a novel THA is proposed to solve the degradation in amplitude and improve the linearity of signal with frequency increasing to giga Hz. A resistive averaging technique is carefully analyzed to relieve noise aliasing. A low-offset latch using a zero-static power dynamic offset cancellation technique is further optimized to realize the requirements of speed, power consumption and noise aliasing. The measurement results reveal that the spurious free dynamic range of the ADC is 30.1 dB even if the input signal is 4.2 GHz sampled at 1.056 GS/s. The core power of the ADC is 30 mW, excluding all of the buffers, and the active area is 0.6 mm 2 . The ADC achieves a figure of merit of 3.75 pJ/conversion-step.

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“…From Ref. [13], the error correction factor (ECF) is defined to give an optimum solution to design the spatial filter, ECF Á…”

Section: Interpolation Network and Resistive Averaging Techniquementioning

confidence: 99%

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-WB receiver

Zhao¹,

Wang²,

Qin³

et al. 2011

J. Semicond.

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Analysis and simulation of distributed T/H with averaging technique in folding and interpolating A/D converters

Zhang

Shao

2009

Circuit Theory & Apps

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SUMMARYDistributed track-and-hold (T/H) circuit is widely used in folding and interpolating analog-to-digital (A/D) converters as a good candidate of single T/H circuits for an optimum overall system performance. But, rigorous analysis and method for design do not exist. This paper brings averaging network to suppress the random offset voltages of the differential difference pre-amplifiers (DDPAs), which locate before T/H circuit featuring two differential inputs for the requirement of fully differential A/D converters. The first contribution of this work is to present the exact expressions for the output voltage and gain in S-domain, the integral nonlinearity (INL) and differential nonlinearity (DNL) in DDPAs through the further insight into this architecture. Furthermore, distortion resulting from settling time limitation, interpolation error, folder offset, and all sources of mismatch in averaged DDPAs is considered. In addition, the figure of merit for INL and DNL is proposed to quantify the effectiveness of averaging and be served as the guideline for the optimum design. Finally, these theoretical results were verified against Hspice simulations from a design example of distributed T/H circuits for 8-bit 250 MHz folding and interpolating A/D converter, which confirmed the accurate and exhaustive analysis and exhibited a good agreement.

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Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

Wang

Dehollain

Hong

2012

Analog Integr Circ Sig Process

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Spatial filtering in flash A/D converters

Cited by 49 publications

References 18 publications

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-WB receiver

A sub-sampling 4-bit 1.056-GS/s flash ADC with a novel track and hold amplifier for an IR-WB receiver

Analysis and simulation of distributed T/H with averaging technique in folding and interpolating A/D converters

Design of a parallel low power flash A/D converter for the sub-sampling IR-UWB receiver

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