CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

Kim, Chan-Kyung; Lee, Jae-Goo; Jun, Young-Hyun; Lee, Chilgee; Kong, Bai-Sun

doi:10.1016/j.mejo.2007.08.003

Cited by 33 publications

(21 citation statements)

References 9 publications

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“…In the proposed sensor, total energy dissipation over a time window, t, can be represented as (3.9) [79] 0.5 μm 0.014 [80] 0.6 μm 0.017 [81] 0.35 μm 0.024 [82] 0.35 μm 0.029 [86] 0.35 μm 0.029 [87] 2 μm 0.009 [88] 0.7 μm 0.014 [89] 0.7 μm 0.021 [90] 0.6 μm 0.014 [91] 80 nm 1.125…”

Section: Adapting Sampling Rate and Resolutionmentioning

confidence: 99%

Managing Temperature Effects in Nanoscale Adaptive Systems

Wolpert

Ampadu

2012

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Section: Adapting Sampling Rate and Resolutionmentioning

confidence: 99%

Managing Temperature Effects in Nanoscale Adaptive Systems

Wolpert

Ampadu

2012

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“…RELATED WORK Past work on DRAM refresh focuses on hardware principles, such as refresh methods (mostly in patents), power enhancements, fault tolerance support or discharge monitoring [3]- [7], [17], [22]. One exception is the work by Moshnyaga et al that utilizes operating system facilities to trade off DRAM vs. flash storage to mitigate current differences in access latencies, bandwidth and power consumption [13].…”

Section: Reduction In Dram Energy Consumptionmentioning

confidence: 99%

Making DRAM refresh predictable

Bhat

Mueller

2011

Real-Time Syst

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Abstract-Embedded control systems with hard real-time constraints require that deadlines are met at all times or the system may malfunction with potentially catastrophic consequences. Schedulability theory can assure deadlines for a given task set when periods and worst-case execution times (WCETs) of tasks are known. While periods are generally derived from the problem specification, a task's code needs to be statically analyzed to derive safe and tight bounds on its WCET. Such static timing analysis abstracts from program input and considers loop bounds and architectural features, such as pipelining and caching. However, unpredictability due to dynamic memory (DRAM) refresh cannot be accounted for by such analysis, which limits its applicability to systems with static memory (SRAM).In this paper, we assess the impact of DRAM refresh on task execution times and demonstrate how predictability is adversely affected leading to unsafe hard real-time system design. We subsequently contribute a novel and effective approach to overcome this problem through software-initiated DRAM refresh. We develop (1) a pure software and (2) a hybrid hardware/software refresh scheme. Both schemes provide predictable timings and fully replace the classical hardware autorefresh. We discuss implementation details based on this design for multiple concrete embedded platforms and experimentally assess the benefits of different schemes on these platforms. The resulting predictable execution behavior in the presence of DRAM refresh combined with the additional benefit of reduced access delays is unprecedented, to the best of our knowledge.

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“…This allows us to clamp VVDD to the value close to a target level regardless of die temperature. Current-starved inverters (INVs) are used in the ROSC to make them less sensitive to VDD fluctuation due to noises [10]. We also assume that quiet analog VDD used for PLLs is applied to the ROSC since it often exhibits only Gaussian white-noise [11].…”

Section: Nbti Tracking Schemementioning

confidence: 99%

Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits

Sinkar

Kim

2010

2010 11th International Symposium on Quality Electronic Design (ISQED)

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Power-gating (PG) techniques have been widely used in modern digital ICs to reduce their standby leakage power during idle periods. Meanwhile, virtual supply voltage (VVDD) of a power-gated IC is a function of strength of a PG device and total current flowing through it. Thus, the VVDD level becomes susceptible to 1) negative bias temperature instability (NBTI) degradation that weakens the PG device over time and 2) temporal temperature variation that affects active leakage current (thus total current) of the IC. To account for the NBTI degradation, the PG device must be upsized such that it guarantees a minimum VVDD level that prevents any timing failure over chip lifetime. Moreover, the PG device is also sized for the worst-case voltage drop partly resulted by a large amount of active leakage current at high temperature. However, increasing the size of the PG device to consider both effects leads to higher VVDD (thus active leakage power) than necessary at low temperature and/or in early chip lifetime. To minimize active leakage power increase due to these effects, we propose two techniques that adjust strength of a PG device based on its usage and IC's temperature at runtime. Both techniques are applied to an experimental setup modeling total current consumption of an IC in 32nm technology and their efficacy is demonstrated in the presence of within-die spatial process and temperature variations. On average of 100 die samples, they can reduce active leakage power by up to 10% in early chip lifetime. KeywordsNegative bias temperature instability, process and temperature variations, power-gating, active leakage power

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CMOS temperature sensor with ring oscillator for mobile DRAM self-refresh control

Cited by 33 publications

References 9 publications

Managing Temperature Effects in Nanoscale Adaptive Systems

Managing Temperature Effects in Nanoscale Adaptive Systems

Making DRAM refresh predictable

Analyzing and minimizing effects of temperature variation and NBTI on active leakage power of power-gated circuits

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