1998
DOI: 10.1049/el:19980320
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CMOS trimming circuit based on polysilicon fusing

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Cited by 12 publications
(7 citation statements)
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“…TiO 2 films were often prepared by using either sol-gel method [19][20][21][22][23][24][25], pray pyrolysis [26] or sputtering [27]. Pulsed laser deposition (PLD) method became a widely used technique during the past few years due to the advantages of a simple system set-up, a wide range of deposition conditions, wide choice of materials and high instantaneous deposition rates [28][29][30][31].…”
Section: Introductionmentioning
confidence: 99%
“…TiO 2 films were often prepared by using either sol-gel method [19][20][21][22][23][24][25], pray pyrolysis [26] or sputtering [27]. Pulsed laser deposition (PLD) method became a widely used technique during the past few years due to the advantages of a simple system set-up, a wide range of deposition conditions, wide choice of materials and high instantaneous deposition rates [28][29][30][31].…”
Section: Introductionmentioning
confidence: 99%
“…Polyfusing OTP using joule heating has also been tried for CMOS analog circuits of on-chip ROM to compensate for the process variations and so on [2], but this is not reliable enough to be used for manufacturing. AF elements are more reliable and have been adopted successfully in some commercial circuits such as the via AF used in field programmable gate array (FPGA) from Actel [3] and oxide-nitride-oxide AF proposed for DRAM cell repairing at package level [4], [5].…”
Section: Introductionmentioning
confidence: 99%
“…Furthermore, most of them require high-voltage programming and extra transistors. Fuse type of OTP using polysilicon [7] or silicide [8], [9] as a fuse to be broken down by electromigration or Joule heating can be programmed using lower voltage, but they usually require a large cell size.…”
mentioning
confidence: 99%