Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

Shi, Min; He, Jin; Zhang, Lining; Ma, Chenyue; Zhou, Xingye; Lou, Haijun; Zhuang, Hao; Wang, Ruonan; Li, Yongliang; Ma, Yong; Wu, Wen‐Wei; Wang, Wenping; Chan, Mansun

doi:10.1109/led.2011.2147754

Cited by 23 publications

(9 citation statements)

References 11 publications

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“…While we maintain the use of scan chains in the design, we assume that they have been disabled through use of a fuse mechanism. The implementation of fuses has been previously demonstrated and widely used in practice [18], [19]. While additional side channel techniques may augment an attacker's capabilities [20], we consider these to be outside the scope of the paper.…”

Section: A Attacker Modelmentioning

confidence: 99%

Latch-Based Logic Locking

Sweeney

Zackriya

Pagliarini

et al. 2020

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

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Globalization of IC manufacturing has led to increased security concerns, notably IP theft. Several logic locking techniques have been developed for protecting designs, but they typically display very large overhead, and are generally susceptible to deciphering attacks. In this paper, we propose latch-based logic locking, which manipulates both the flow of data and logic in the design. This method converts an interconnected subset of existing flip-flops to pairs of latches with programmable phase. In tandem, decoy latches and logic are added, inhibiting an attacker from determining the actual design functionality. To validate this technique, we developed and verified a locking insertion flow, analyzed PPA and ATPG overhead on benchmark circuits and industry cores, extended existing attacks to account for the technique, and taped out a demonstration chip. Importantly, we show that the design overhead with this approach is significantly less than with previous logic locking schemes, while resisting model checker-based, oracle-driven attacks. With minimal delay overhead, large numbers of decoy latches can be added, cheaply increasing attack resistance.

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Section: A Attacker Modelmentioning

confidence: 99%

Latch-Based Logic Locking

Sweeney

Zackriya

Pagliarini

et al. 2020

2020 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)

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“…Therefore, a change in the key requires modifying the mask layout. Efuse [1] and anti-fuse [2,3] are one-time programmable (OTP) memories, which can be built in a generic digital process, but the programming operation is irreversible. A battery-backed SRAM is a power-gated SRAM in data retention mode.…”

Section: Introductionmentioning

confidence: 99%

Serial RRAM Cell for Secure Bit Concealing

et al. 2021

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Non-volatile memory cells are exposed to adversary attacks since any active countermeasure is useless when the device is powered off. In this context, this work proposes the association of two serial RRAM devices as a basic cell to store sensitive data, which could solve this bothersome problem. This cell has three states: ‘1’, ‘0’, and masked. When the system is powered off or the data is not used, the cell is set to the masked state, where the cell still stores a ‘1’ or a ‘0’ but a malicious adversary is not capable of extracting the stored value using reverse engineering techniques. Before reading, the cell needs to be unmasked and it is masked afterwards until the next reading request. The operation of the cell also provides robustness against side-channel attacks. The presented experimental results confirm the validity of the proposal.

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“…It changes in gate material, finshape bulk and lack of an RPO layer reduce the scalability of the logic-compatible RRAM mentioned above. [19][20][21][22] As a result, novel structures for the 3D FinFET process are needed to develop fully compatible NVM cells.…”

Section: Introductionmentioning

confidence: 99%

Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

Shih¹,

Hsu²,

King³

et al. 2018

Jpn. J. Appl. Phys.

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A via resistive random access memory (RRAM) cell fully compatible with the standard CMOS logic process has been successfully demonstrated for high-density logic nonvolatile memory (NVM) modules in advanced FinFET circuits. In this new cell, the transition metal layers are formed on both sides of a via, given two storage bits per via. In addition to its compact cell area (1T + 14 nm ' 32 nm), the twin-bit via RRAM cell features a low operation voltage, a large read window, good data retention, and excellent cycling capability. As fine alignments between mask layers become possible, the twin-bit via RRAM cell is expected to be highly scalable in advanced FinFET technology.

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Zero-Mask Contact Fuse for One-Time-Programmable Memory in Standard CMOS Processes

Cited by 23 publications

References 11 publications

Latch-Based Logic Locking

Latch-Based Logic Locking

Serial RRAM Cell for Secure Bit Concealing

Twin-bit via resistive random access memory in 16 nm FinFET logic technologies

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