2017 6th International Symposium on Next Generation Electronics (ISNE) 2017
DOI: 10.1109/isne.2017.7968735
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CMOS VCO with three-path inductor

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Cited by 3 publications
(2 citation statements)
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“…There are many approaches to reduce phase noise. In [8,9], designing a three-path inductor with a suitable quality factor, phase noise was greatly improved, but this structure increases the chip area, and on the other hand, in this approach BiCMOS as an expensive technology is used. Therefore, this structure is not suitable for IoT applications.…”
Section: Introductionmentioning
confidence: 99%
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“…There are many approaches to reduce phase noise. In [8,9], designing a three-path inductor with a suitable quality factor, phase noise was greatly improved, but this structure increases the chip area, and on the other hand, in this approach BiCMOS as an expensive technology is used. Therefore, this structure is not suitable for IoT applications.…”
Section: Introductionmentioning
confidence: 99%
“…In some circuits, current-reuse structures have been used to increase the main core G m without increasing the high current consumption [8,9]. Using this structure, the G m value is almost doubled and it improves phase noise, so the power consumption becomes lower than before.…”
Section: Introductionmentioning
confidence: 99%