CMOS VLSI subsystems for low-voltage low-power applications

Abstract

My journey of PhD candidature at NTU has been a worthwhile experience, which is both challenging and fulfilling. In fact, in every important passage of our lives, there are always bound to be some special individuals whose support and contribution are essential in determining our success or failure. In my endeavor of pursuing PhD, the first person to whom, I want to thank is none other than my dissertation advisor, Associate Professor Yeo Kiat Seng. I would like to express my deepest gratitude to him for his willingness and readiness to invest time into giving me adequate and timely guidance despite his very tight schedule. The numerous discussion and brainstorming sessions with him were intellectually inspiring and enlightening. The continuous support and confidence he bestowed upon me was invaluable in steering this dissertation to completion through all its phases. It is also my great pleasure to express my heartfelt appreciation to Associate Professor Chang Chip Hong for sharing his expertise with me and providing insightful comments on my research work. I would like to extend my special thanks to the technical staffs of the Centre for Integrated Circuits and Systems (CICS), Mr. Sia Liang Poo, Mr. Jimmy, and Mr. William for the countless help and assistance they have been offering me throughout my stay in the laboratory. Next, to my peers Gu Jiangmin, Phyu Myint Wai, Chia Leong Yap, Li Qiang, He Yajuan, and Liu Haiqi, thanks for your genuine acquaintance and I will never forget the many wondrous moments we have spent together. The beautiful moments will be forever fresh in mind. Last but not least, I would like to convey my heartfelt appreciation to my parents, siblings and my loved ones for steadfastly standing by me throughout the years, through thick and thin. Words can never express the warmth and thankfulness I feel for each one of them. I want to thank my dear husband, Kam Chew, for his enormous support and endless love, patience and encouragement. The unwavering trust and wholehearted support he has given me all this while will be eternally engraved into my memory. With this, I dedicate this doctorate to them.

Design of low-voltage low-power nano-scale SRAMs

“…Power dissipated in an SRAM can be categorized into two components: active (or dynamic) power and standby (or leakage) power [37]. Each of these components comes from the memory array, the decoders and the periphery circuits such as write drivers, SA and the pre-charge circuits, etc.…”

“…Each of these components comes from the memory array, the decoders and the periphery circuits such as write drivers, SA and the pre-charge circuits, etc. The standby power is dominated by the leakage current from the memory array, thus, static current from other sources can be ignored [37]. The active and standby power of an m x n-bit SRAM can be expressed as follows: CPT: is the capacitance of the logic and driving circuits in the periphery.…”

“…This draws some unnecessary power consumption. In fact, low-power SRAM designs can utilize smaller-than-50%-duty cycle and half-V DD pulse to reduce the power dissipated from these heavily capacitive lines [37,71]. Positive and negative pulses can be used concurrently to overcome the reduced gate-overdrive at the receiver ends of the signals [37,72].…”

“…In fact, low-power SRAM designs can utilize smaller-than-50%-duty cycle and half-V DD pulse to reduce the power dissipated from these heavily capacitive lines [37,71]. Positive and negative pulses can be used concurrently to overcome the reduced gate-overdrive at the receiver ends of the signals [37,72]. However, this technique is not very widely used in the sub-100 nm technologies since the corresponding power supply is scaled to near 1V, half of which is very close to the threshold border, resulting in an extremely weak current drive-ability.…”

“…However, this factor is becoming less dominant as technology advances to the nanometer regime. When the MOS individual column and row sub-decoder [28,37]. Therefore, circuit designers must consider the area-power consumption trade-off to obtain the optimum partitioning.…”