CMOS wideband LNA design using integrated passive device

Chen, Hsien‐Ku; Hsu, Yuan-Chia; Lin, Tzu Chau; Chang, Der–Chen; Juang, Ying‐Zong; Lu, Shey‐Shi

doi:10.1109/mwsym.2009.5165786

Cited by 17 publications

(9 citation statements)

References 11 publications

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“…This input conductance is further set equal to the source conductance for achieving input impedance matching. Under this matching condition, the noise factor of a single mixer excluding the PD linearizer is derived as (12) where , , and are the output load of the mixer, the bias current of , and the amplitude of the LO signal, respectively. Injecting a current-bleeding current into the switching stage of the mixer shown in Fig.…”

Section: B Down-conversion Mixer With a Pd Linearizermentioning

confidence: 99%

Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices

Horng

2014

IEEE Trans. Microwave Theory Techn.

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This paper presents a stacked RF front-end (RFE) package for wideband receiver applications. While having a power consumption of 18 mW, the flipped CMOS chip consisting of a lownoise amplifier and a quadrature down-conversion mixer stacks on a glass integrated passive device (GIPD) substrate, subsequently achieving a noise figure of 2.2-2.8 dB and a conversion gain of 23-25 dB over 1-6 GHz. Moreover, the RFE package uses a GIPD balun with a high common-mode rejection ratio and a post-distortion linearizer in the CMOS mixer, subsequently resulting in an of 57-68 dBm and an of 5.2-3.5 dBm over the entire operating band. This paper also elucidates how coupling between the flipped CMOS chip and GIPD balun affects the RFE linearity. Fabricated with 0.18-m CMOS technology, the flipped CMOS chip is packaged on the GIPD substrate with a footprint area of 1.8 1.8 mm .

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Section: B Down-conversion Mixer With a Pd Linearizermentioning

confidence: 99%

Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices

Horng

2014

IEEE Trans. Microwave Theory Techn.

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“…The CMOS chip is connected to the IPD inductor using flip-chip technology. An equivalent circuit model of the solder bumps that connect the CMOS chip with the IPD inductor was synthesized in the previous work [11] and is used in the design of the CMOS-IPD VCO.…”

Section: Glass Substratementioning

confidence: 99%

“…Modules that combine active chips and IPD substrate with the flip-chip or the wire-bonding technology have also been presented [8]- [10]. Our previous work [11] proposed a CMOS wide-band LNA design using IPD technology to implement the input matching inductor and the high-inductance RFC. Comparison between the simulated and the measured results showed good agreement.…”

Section: Introductionmentioning

confidence: 99%

Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies

Hsu

Chiou

Chen

et al. 2011

IEEE Trans. Compon., Packag. Manufact. Technol.

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This paper presents two voltage controlled oscillators (VCOs) operating at 5.42 and 5.76 GHz implemented in 0.18-µm complementary metal-oxide semiconductor (CMOS) technology with integrated passive device (IPD) inductors. One IPD inductor was stacked on the top of the active region of the 5.76-GHz VCO chip, whereas the other IPD inductor was placed on the top of the 5.42-GHz VCO CMOS chip but far from the its active region. The high-quality IPD inductors reduce the phase noise of the VCOs. The measurements of the two VCOs indicate the same phase noise of −120 dBc/Hz at 1 MHz offset frequency. These results demonstrate a 6-dB improvement compared to the VCO using an on-chip inductor. This paper also presents the effect of the coupling between the IPD inductor and the active region of the chip on the phase noise performance. Index Terms-Complementary metal-oxide semiconductor, flip-chip, integrated passive device, phase noise, voltage controlled oscillator.

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“…(SiP) has been ces off the chip but assive device (IPD) assive components arge expensive die nventionally [1][2][3][4][5][6]. ntegral part of the ve devices can be , GaN devices for w-noise amplifiers) cost [7][8]. Fig.…”

Section: Introductionmentioning

confidence: 99%

High performance integrated passive devices (ipds) on low cost through silicon interposer (LC-TSI)

Cheng

Zheng

Liu

et al. 2013

2013 IEEE 15th Electronics Packaging Technology Conference (EPTC 2013)

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This paper presents the design, characterization of integrated passive devi cost through silicon interposer (LC-TSI). T symmetrical spiral inductors is presented an paper. The effect of space between traces an trace on the Q-factor are studied. In addi with TSV around and under are also disc platform, some radio-frequency (RF) IPDs including a millimeter-wave (mmWave) a 77 GHz for the automotive radar application based on the quarter-mode substrate inte (QMSIW) is also designed on the T performance of these structures is given an that the TSI platform is an attractive and pr a carrier to design IPDs and RF-IPD frequency.Keywords-Bandpass filter (BPF), integra (IPD), low-cost through silicon interposer (L wave (mmWave).

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CMOS wideband LNA design using integrated passive device

Cited by 17 publications

References 11 publications

Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices

Low-Noise and High-Linearity Wideband CMOS Receiver Front-End Stacked With Glass Integrated Passive Devices

Low Phase Noise and Low Power Consumption VCOs Using CMOS and IPD Technologies

High performance integrated passive devices (ipds) on low cost through silicon interposer (LC-TSI)

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