CMUT fabrication based on a thick buried oxide layer

Abstract

We introduce a versatile fabrication process for direct wafer-bonded CMUTs. The objective is a flexible fabrication platform for single element transducers, 1D and 2D arrays, and reconfigurable arrays. The main process features are: A low number of litho masks (five for a fully populated 2D array); a simple fabrication sequence on standard MEMS tools without complicated wafer handling (carrier wafers); an improved device reliability; a wide design space in terms of operation frequency and geometric parameters (cell diameter, gap height, effective insulation layer thickness); and a continuous front face of the transducer (CMUT plate) that is connected to ground (shielding for good SNR and human safety in medical applications). All of this is achieved by connecting the hot electrodes individually through a thick buried oxide layer, i.e. from the handle layer of an SOI substrate to silicon electrodes located in each CMUT cell built in the device layer. Vertical insulation trenches are used to isolate these silicon electrodes from the rest of the substrate. Thus, the high electric field is only present where required -in the evacuated gap region of the device and not in the insulation layer of the post region. Array elements (1D and 2D) are simply defined be etching insulation trenches into the handle wafer of the SOI substrate.

A 1-MHz 2-D CMUT array for HIFU thermal ablation

“…We finished the fabrication of a 2-D CMUT array using the thick-buried-oxide (BOX) fabrication process [5]. Figure 1 shows pictures of the finished 2-D CMUT array, which has 20 × 20 CMUT elements with an element-toelement pitch of 1 mm × 1 mm and an operating center frequency of 1 MHz.…”

2-D row-column CMUT arrays with an open-grid support structure

“…As covered in previous work in the literature, such a design can be realized using silicon-oninsulator (SOI) wafers with BOX layers that can support high voltages [5]. A second criterion is that the contact pads to the row-and column elements are accessible from the perimeter of the array.…”

“…This dictates a wafer-bonding approach as originally suggested by Huang et. al [2] and used in later processes involving BOX insulation layers [5].…”

“…Therefore, various designs have been suggested in the literature that seek to combine small vacuum gap spacings and extended structural posts able to withstand high voltages, e.g. through LOCOS oxidation or buried oxides [4], [5]. The latter process offers the highest degree of insulation, since the bottom electrode rests on a buried oxide (BOX) layer, the thickness of which can be chosen independently of the desired vacuum gap size.…”

“…The latter process offers the highest degree of insulation, since the bottom electrode rests on a buried oxide (BOX) layer, the thickness of which can be chosen independently of the desired vacuum gap size. If such a process is used to fabricate fully populated 2-D arrays, through wafer vias are needed in order to access the bottom electrode [5]. This complicates the fabrication process considerably if the arrays are to be operated in the MHz range, where the via diameter is limited by the pitch of the closely spaced CMUT elements.…”