Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting

Abstract

Abstract

Reducing random-dopant fluctuation impact using footer transistors in many-core systems

“…One of the other considerations is the impact on the performance. In the literature, the footer transistor used to increase the total threshold voltage, which results in an increase in gate switching delay [27,28]. However, the proposed method in this paper does not attempt to increase the total threshold voltage.…”

“…However, it might not be practical to implement a single transistor for an entire large core [23,27]. Different methods in the literature proposed footer transistor sizing in a multi-core platform.…”

“…In fact, area is considered free compared to power and speed design goals [26]. Thus, using footer transistor is becoming a common practice to reduce power consumption despite the area overhead [27].…”

Optimal power switch design for dynamic voltage scaling from high performance to subthreshold operation

“…Power switch sizing methodologies have been examined in depth to support techniques like multi-threshold CMOS (MTCMOS), which used high-V T power switches to reduce leakage [3]. Optimal power switch design for has been extensively explored, e.g., [4]- [7]. These schemes explore ways to optimize Ion/ Ioff and develop methodologies or tools to implement these schemes.…”

Towards Process Variation-Aware Power Gating

“…As this is the sure price to pay for power gating, a penalty limit has to be set. In this paper, we take 10% performance loss as the limit and determine the total size of the power switches [17], [18]. From there, we can break the sizes into individual power switches as in the works of [5], [8]- [10].…”