Coarse-grained Structural Placement for a Synthesized Parallel Multiplier

Abstract

We propose a new coarse-grained structural placement methodology tightly coupled with logic synthesis to exploit inherent structure of a synthesized parallel multiplier. The proposed method takes advantage of both benefits of logic optimizations and remaining regularity in the synthesized netlist. This is achieved by using a structural template of the multiplier, which is considered to be provided by dedicated datapath generators in the logic synthesis. The template includes primary input and output nets and structural specification of the multiplier, which is used to infer structural relative locations of a partial netlist and then structurally map the partial cells to guide structural placement of the rest of the module. Comparing to a conventional P&R (Place and Route) methodology, it improves the critical path delay, the total negative slacks, and the total wirelength by 2%, 42%, and 2%, respectively, on datapath intensive industrial designs.