Code Density and Energy Efficiency of Exposed Datapath Architectures

Jääskeläinen, Pekka; Kultala, Heikki; Viitanen, Timo; Takala, Jarmo

doi:10.1007/s11265-014-0924-x

Cited by 28 publications

(18 citation statements)

References 23 publications

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“…In addition to various academic TTA designs, the authors know about two that are advertised in commercial products [KDPOF 2014;Maxim Integrated Products, Inc. 2004], and of multiple designs fabricated to test chips but not yet sold or published. Furthermore, several commercial designs contain other variations of the "exposed datapath" concept that can benefit from the model described in this article [Jääskeläinen et al 2015].…”

Section: Transport Triggered Programming Modelmentioning

confidence: 99%

“…Constraint satisfaction problems are typically NP-hard [Mackworth 1977], and many important constraint satisfaction problems have been proven to be NP-complete [Rossi et al 2006]. In particular, ILP is NP-hard [Jongen et al 2004] and 0 -1 integer programming is NP-complete [Karp 1972]. Therefore, compiler algorithms utilizing ILP are not generally applicable, but they are usually used for only the most important parts of the program with feasible size.…”

Section: Integer Linear Programming Fundamentalsmentioning

confidence: 99%

“…Transport Triggered Architectures (TTAs) and other so-called exposed datapath architectures [Jääskeläinen et al 2015] reveal even more details of the datapath under the control of the software. For TTA, the main benefits are in reducing the register file pressure, which allows more energy-efficient and scalable designs due to the reduced general-purpose register file bottleneck.…”

Section: Introductionmentioning

confidence: 99%

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Integer Linear Programming-Based Scheduling for Transport Triggered Architectures

Äijö

Jääskeläinen

Elomaa

et al. 2015

ACM Trans. Archit. Code Optim.

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Static multi-issue machines, such as traditional Very Long Instructional Word (VLIW) architectures, move complexity from the hardware to the compiler. This is motivated by the ability to support high degrees of instruction-level parallelism without requiring complicated scheduling logic in the processor hardware. The simpler-control hardware results in reduced area and power consumption, but leads to a challenge of engineering a compiler with good code-generation quality. Transport triggered architectures (TTA), and other so-called exposed datapath architectures, take the compiler-oriented philosophy even further by pushing more details of the datapath under software control. The main benefit of this is the reduced register file pressure, with a drawback of adding even more complexity to the compiler side. In this article, we propose an Integer Linear Programming (ILP)-based instruction scheduling model for TTAs. The model describes the architecture characteristics, the particular processor resource constraints, and the operation dependencies of the scheduled program. The model is validated and measured by compiling application kernels to various TTAs with a different number of datapath components and connectivity. In the best case, the cycle count is reduced to 52% when compared to a heuristic scheduler. In addition to producing shorter schedules, the number of register accesses in the compiled programs is generally notably less than those with the heuristic scheduler; in the best case, the ILP scheduler reduced the number of register file reads to 33% of the heuristic results and register file writes to 18%. On the other hand, as expected, the ILP-based scheduler uses distinctly more time to produce a schedule than the heuristic scheduler, but the compilation time is within tolerable limits for production-code generation. CCS Concepts: r Mathematics of computing → Integer programming; r Computer systems organization → Very long instruction word; r Software and its engineering → Compilers

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Section: Transport Triggered Programming Modelmentioning

confidence: 99%

Section: Integer Linear Programming Fundamentalsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Integer Linear Programming-Based Scheduling for Transport Triggered Architectures

Äijö

Jääskeläinen

Elomaa

et al. 2015

ACM Trans. Archit. Code Optim.

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“…Using local register files connected to processing elements: Reduces the overhead of accessing centralized general-purpose register files. This solution is also used in other approaches [8,9,16,20,31,32]. 5.…”

Section: Eliminating the Need For Intermediate Dfg Generationmentioning

confidence: 99%

“…Assuming two operand instructions (algorithm lines [13][14][15][16][17][18][19][20][21][22]. There are three cases: (1) two inputs; (2) one input and one RAW; and (3) two RAWs.…”

Section: Bt Ms Algorithmmentioning

confidence: 99%

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Ferreira

Denver

Pereira

et al. 2015

J Sign Process Syst

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In the past years, many works have demonstrated the applicability of Coarse-Grained Reconfigurable Array (CGRA) accelerators to optimize loops by using software pipelining approaches. They are proven to be effective in reducing the total execution time of multimedia and signal processing applications. However, the run-time reconfigurability of CGRAs is hampered overheads introduced by the needed translation and mapping steps. In this work, we present a novel run-time translation technique for the modulo scheduling approach that can convert binary code onthe-fly to run on a CGRA. We propose a greedy approach, since the modulo scheduling for CGRA is an NP-complete problem. In addition to read-after-write dependencies, the dynamic modulo scheduling faces new challenges, such as register insertion to solve recurrence dependences and to balance the pipelining paths. Our results demonstrate that the greedy run-time algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for a 16-issue VLIW processor. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated. In this analysis it is demonstrated R. Ferreira ( ) · W. Denver that when changing from one memory access per cycle to two memory accesses per cycle, the modulo scheduling algorithm is able to exploit this increase in memory bandwidth and enhance performance accordingly. Additionally, to measure area and performance, the proposed CGRA was prototyped on an FPGA. The area comparisons show that a crossbar CGRA (with 16 processing elements and including an 4-issue VLIW host processor) is only 1.11 × bigger than a standalone 8-issue VLIW softcore processor.

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Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments

Gesper

Weißbrich

Nolting

et al. 2019

Lecture Notes in Computer Science

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Microcontrollers to be used in harsh environmental conditions, e.g., at high temperatures or radiation exposition, need to be fabricated in robust technology nodes in order to operate reliably. However, these nodes are considerably larger than cutting-edge semiconductor technologies and provide less speed, drastically reducing system performance. In order to achieve low silicon area costs, low power consumption and reasonable performance, the processor architecture organization itself is a major influential design point. Parameters like data path width, instruction execution paradigm, code density, memory requirements, advanced control flow mechanisms etc., may have large effects on the design constraints. Application characteristics, like exploitable data parallelism and required arithmetic operations, have to be considered in order to use the implemented processor resources efficiently. In this paper, a design space exploration of five different architectures with MIPS-or ARM-compatible instruction set architectures, as well as transport-triggered instruction execution is presented. Using a 0.18 lm SOI CMOS technology for high temperature and an exemplary case study from the fields of communication, i.e., powerline communication encoder, the influence of architectural parameters on performance and hardware efficiency is compared. For this application, a transporttriggered architecture configuration has an 8.5Â higher performance and 2.4Â higher computational energy efficiency at a 1.6Â larger total silicon area than an off-the-shelf ARM Cortex-M0 embedded processor, showing the considerable range of design trade-offs for different architectures.

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Code Density and Energy Efficiency of Exposed Datapath Architectures

Cited by 28 publications

References 23 publications

Integer Linear Programming-Based Scheduling for Transport Triggered Architectures

Integer Linear Programming-Based Scheduling for Transport Triggered Architectures

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Evaluation of Different Processor Architecture Organizations for On-site Electronics in Harsh Environments

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