Integer Linear Programming-Based Scheduling for Transport Triggered Architectures

Abstract

Static multi-issue machines, such as traditional Very Long Instructional Word (VLIW) architectures, move complexity from the hardware to the compiler. This is motivated by the ability to support high degrees of instruction-level parallelism without requiring complicated scheduling logic in the processor hardware. The simpler-control hardware results in reduced area and power consumption, but leads to a challenge of engineering a compiler with good code-generation quality. Transport triggered architectures (TTA), and other so-called exposed datapath architectures, take the compiler-oriented philosophy even further by pushing more details of the datapath under software control. The main benefit of this is the reduced register file pressure, with a drawback of adding even more complexity to the compiler side. In this article, we propose an Integer Linear Programming (ILP)-based instruction scheduling model for TTAs. The model describes the architecture characteristics, the particular processor resource constraints, and the operation dependencies of the scheduled program. The model is validated and measured by compiling application kernels to various TTAs with a different number of datapath components and connectivity. In the best case, the cycle count is reduced to 52% when compared to a heuristic scheduler. In addition to producing shorter schedules, the number of register accesses in the compiled programs is generally notably less than those with the heuristic scheduler; in the best case, the ILP scheduler reduced the number of register file reads to 33% of the heuristic results and register file writes to 18%. On the other hand, as expected, the ILP-based scheduler uses distinctly more time to produce a schedule than the heuristic scheduler, but the compilation time is within tolerable limits for production-code generation. CCS Concepts: r Mathematics of computing → Integer programming; r Computer systems organization → Very long instruction word; r Software and its engineering → Compilers

Prebypass: Software Register File Bypassing for Reduced Interconnection Architectures

“…The scheduling algorithms based on integer linear programming [19] results in aggressive bypassing since they are immune to the scheduling order of the nodes. However, their use is limited to very small programs because of their extremely long scheduling time.…”

Optimal Scheduling for Exposed Datapath Architectures with Buffered Processing Units by ASP

“…These architectures usually contain a large number of PUs with local storage. However, their current compiler technology (Lee et al 1998;Smith et al 2006;Aijö et al 2016;Guo et al 2006;Schilling et al 2009), although utilizing register bypassing, still relies on classic code generators where the use of a minimal number of registers is in the focus rather than maximizing the degree of ILP. In , we therefore suggested a code generation technique for exposed datapath architectures that is based on a breadth-first traversal rather than the classic depth-first traversal (Sethi and Ullman 1970) over the syntax trees.…”