Coherent Hole Transport in Selective Area Grown Ge Nanowire Networks

Abstract

Holes in germanium nanowires have emerged as a realistic platform for quantum computing based on spin qubit logic. On top of the large spin−orbit coupling that allows fast qubit operation, nanowire geometry and orientation can be tuned to cancel out charge noise and hyperfine interaction. Here, we demonstrate a scalable approach to synthesize and organize Ge nanowires on silicon (100)-oriented substrates. Germanium nanowire networks are obtained by selectively growing on nanopatterned slits in a metalorganic vapor phase epitaxy system. Low-temperature electronic transport measurements are performed on nanowire Hall bar devices revealing high hole doping of ∼10 18 cm −3 and mean free path of ∼10 nm. Quantum diffusive transport phenomena, universal conductance fluctuations, and weak antilocalization are revealed through magneto transport measurements yielding a coherence and a spin−orbit length of the order of 100 and 10 nm, respectively.

The implementation of thermal and UV nanoimprint lithography for selective area epitaxy

“…Once we achieved high-quality, uniform regions, we demonstrated the general applicability of the method by growing in-plane NWs. Following the pattern transfer to the SiO 2 layer, the substrate is loaded to the MOVPE reactor, and Ge NWs are grown as explained in detail in [28]. SEM micrograph in figure 3(c) confirms the uniformity of the structures (see also figure S7).…”

“…Previously, we demonstrated the growth of in-plane (horizontal) NWs, as well as NW junctions by SAE using EBL to define the nanoscale patterns [26][27][28][29]. Moreover, SAE of vertical NWs has been performed on the NIL patterned substrates [30][31][32].…”

Electronic Transport and Quantum Phenomena in Nanowires

“…Although selective-area growth has been used for the growth of large-areas of Si and Ge, it is unexplored for the growth of Ge/Si core/shell nanowire structures. In a first report on the SAG of Ge nanowires on Si(100), the Si surface was conditioned by As to create an oxide-free surface. The resulting wires have a 80 nm diameter, and the remaining challenge is to realize smaller dimensions to avoid inelastic strain relaxation by the creation of crystal defects.…”

Strain-induced ordered Ge(Si) hut wires on patterned Si (001) substrates

“…The incorporation of a metal catalyst in VLS growth is another challenge for quantum devices, as it leads to decreased carrier mobility, parasitic channels and charge noises. 21,22 The direct growth of in-plane Ge NWs and NW-networks has been demonstrated via selective area growth 23 recently, but the crystalline imperfections such as dislocations and stacking faults still remain unsolved. By combining top-down fabrication and bottom-up self-assembly methods, site-controlled Ge hut wires (HWs) with perfect crystal quality have been previously demonstrated along the edges of pre-patterned trenches.…”