Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs

Chiang, Hung-Li; Chen, T. C.; Wang, J. F.; Mukhopadhyay, Subhadeep; Lee, W. K.; Chen, C. L.; Khwa, Win-San; Pulicherla, B.; Liao, Po‐Yung; Su, Kuan-Wei; Yu, K.F.; Wang, T.; Wong, Hei; Diaz, C.H.; Cai, Jin

doi:10.1109/vlsitechnology18217.2020.9265065

Cited by 44 publications

(24 citation statements)

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“…We use the above developed BSIM4 models to tune the threshold voltage across temperatures so that the devices have same subthreshold leakage current IOFF. This is done by reducing the Vth at lower temperature so as to maximize the headroom or overdrive (Vov = Vgs -Vth) and increase the ON materials are amongst a few methods to achieve such Vth tuning [15]. For the rest of the paper, we use the Vth engineered BSIM4 models for our analysis and refer to it as "Iso-IOFF models".…”

Section: F Threshold Voltage Tuning For Iso-leakage Modelsmentioning

confidence: 99%

“…With remarkable improvement in the device behavior including ultra-low leakage current, higher ON current, nearideal subthreshold swing, lower thermal noise and lower device and interconnect resistance [22], Cryo-CMOS has shown promising results for achieving higher performance and/or obtaining better power efficiency [2], [15]. Design requires well calibrated transistor models for low temperature operation, that can be used for circuit level simulations.…”

Section: Introductionmentioning

confidence: 99%

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Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Saligram

Chakraborty

Cao

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in cryogenic operation of digital logic. In this paper, we analyze digital standard cells in 28nm High-K Metal Gate (HKMG) CMOS foundry Process Design Kit (PDK). We have developed BSIM4 models of cryogenic CMOS and calibrated with experimental measurements. Since, low temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this paper, we present inverter static and dynamic characteristics and multiple Ring Oscillator(RO) structures. The simulation study shows that we can achieve 28%(FO4-RO) -59%(NAND3-RO) higher performance under iso-VDD scenario and up to 90% improvement in the Energy Delay Product (EDP) under isooverdrive scenario at 6K compared to room temperature.

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Section: F Threshold Voltage Tuning For Iso-leakage Modelsmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Saligram

Chakraborty

Cao

et al. 2021

IEEE J. Explor. Solid-State Comput. Devices Circuits

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“…Low temperature environment enhances performance of CMOS devices through the improvement of the carrier mobility, subthreshold slope, Cu wire resistance, and thermal noise [1][2][3]. Applications of "cold" CMOS range from high-performance computing to space exploration and low temperature physics.…”

Section: Introductionmentioning

confidence: 99%

Variable-Temperature Noise Characterization of N-MOSFETs Using an In-Situ Broadband Amplifier

Ohmori¹,

Amakawa²

2021

IEEE J. Electron Devices Soc.

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Characterization of broadband noise of MOSFETs from room temperature down to 120 K in fine temperature steps is presented. A MOSFET is mounted on a reusable printed circuit board vehicle with a built-in low-noise amplifier, and the vehicle is loaded into a cryogenic chamber. The vehicle allows noise measurement in the frequency range from 50 kHz to 100 MHz. At low frequencies, it enables extraction of activation energies associated with electron trapping sites. At high frequencies, as has been suggested by noise figure measurements, the white noise of MOSFETs is shown to be dominated by the shot noise, which has much weaker temperature dependence than the thermal noise. The shot noise will be a problematic noise source in broadband RF CMOS circuits operating at cryogenic temperatures.

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“…Due to such dynamic nature of storage, retention time is the key metric for augmented bit-cells. Furthermore, the retention time shows a strong dependence on temperature and makes our proposed cells interesting for cryo-computing applications [19]. Table I-II mentions the retention time for various temperatures.…”

Section: Resultsmentioning

confidence: 95%

Augmented Memory Computing: Dynamically Augmented SRAM Storage for Data Intensive Applications

Sheshadri,

Vijayakumar,

Jacob

et al. 2021

Preprint

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The emergence of various data-intensive applications like artificial intelligence, machine learning etc., has highlighted the energy and throughput bottlenecks inherent in existing computing systems. Memory storage is a major component for such data intensive computational platforms. Consequently, memory-centric research investigations to improve the overall energy-efficiency and throughput of a given computing chip is being actively pursued. Exploration of novel memory technologies for high-density on-chip memories and in-memory computing are the key examples of such memory-centric approaches. In this paper, we propose a novel memory-centric scheme based on CMOS SRAM. Our proposal aims at dynamically increasing the on-chip memory storage capacity of SRAM arrays on-demand. The proposed scheme called -Augmented Memory Computing allows an SRAM cell to operate in two different modes 1) the Normal mode and 2) the Augmented mode. In the Normal mode of operation, the SRAM cell functions like a standard 6 transistor (6T) SRAM cell, storing one bit of data in static format. While in the Augmented mode, each SRAM cell can store >1 bit of data (in a dynamic fashion). Specifically, we propose two novel SRAM cells -an 8 transistor (8T) dual bit storage augmented cell and a 7 transistor (7T) ternary bit storage augmented cell. The proposed 8T dual bit SRAM cell when operated in the Augmented mode, can store a static bit of data while also, simultaneously, storing another bit in a dynamic form. Thus, when operated in Augmented mode, the 8T SRAM cell can store two bits of dataone SRAM-like data and one DRAM-like data, thereby increasing or augmenting the memory storage capacity. On the other hand, the proposed 7T ternary bit storage augmented cell can either store a single SRAM data in Normal mode or can be configured to operate in Augmented mode, wherein it can store ternary data (3 levels (0,0), (0,1), (1,0)) in a dynamic manner. Thus, based on the mode of operation, the proposed augmented memory bitcells can either store one static bit of data or >1 bit of data in a dynamic format. We show the feasibility of our proposed bit-cells through extensive simulations at Globalfoundries 22nm FDX node. It is worth mentioning, the novel scheme of augmented memory bit-cells can be seamlessly combined with existing inmemory computing approaches for added energy and throughput benefits.

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Cold CMOS as a Power-Performance-Reliability Booster for Advanced FinFETs

Cited by 44 publications

References 0 publications

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Power Performance Analysis of Digital Standard Cells for 28 nm Bulk CMOS at Cryogenic Temperature Using BSIM Models

Variable-Temperature Noise Characterization of N-MOSFETs Using an In-Situ Broadband Amplifier

Augmented Memory Computing: Dynamically Augmented SRAM Storage for Data Intensive Applications

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