Combining Clock and Voltage Noise Countermeasures Against Power Side-Channel Analysis

Lagasse, J.; Bartoli, C.; Burleson, Wayne

doi:10.1109/asap.2019.00009

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Cited by 7 publications

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“…Lagasse et al [53] proposed the combination of two methods for generating noise and randomness in the execution of the Advanced Encryption Standard (AES) cryptographic algorithm implemented in hardware and prototyped in FPGA. The first method is to use a random clock, i.e.…”

Section: B Hiding: Random Consumptionmentioning

confidence: 99%

Hardware Countermeasures against Power Analysis Attacks: a Survey from Past to Present

Soares

Lima

Lellis

et al. 2021

JICS

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Modern cryptographic circuits are increasingly demanding security requirements. Since its invention, power analysis attacks are a threat to the security of such circuits. In order to contribute to the design of secure circuits, designers may employ countermeasures in different abstraction levels. This work presents a brief survey of countermeasures to help designers to find good solutions for the design of secure cryptographic systems. A summary is highlighted to compare the pros and cons of the approaches to help designers choose a better solution, or even provide subsidies so that new solutions can be proposed.

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Section: B Hiding: Random Consumptionmentioning

confidence: 99%